I have two Sensors S1 and S2, S1 is a 24v inductive proximity sensor which i isolated using octocoupler to work at 5v and S2 is a transmissive type phototransistor sensor, both are placed at a fixed distance , signal from S1 will is always triggered periodically and used for reference but if the product is defective S2 will not be triggered.

I have to catch if S2 does'nt trigger within 0.9 seconds S1 is triggered.

My initial idea is to use XOR but there is a time difference delay i.e S1 and S2 might not be simultanious. How should i acheive this without a microcontroller.

Instead of XOR if i use a 555 timer with the required time interval and trigger the pin 2 of 555 with S1 and use S2 to retrigger to keep 555 output always high and when S2 fails will the output from pin 3 goes low? but i think retrigger from S2 will be considered same as debounce of S1

         _                  _
S1  ____| |________________| |_____________
S2  _________| |___________________________
Error ___________________________|    |____

Figure 1 by @Transistor for OP to edit.

  • \$\begingroup\$ Can you rephrase your question? What are the output levels now for S2 and S1 when they are active (triggered) and not triggered.. can you draw waveforms on paper and add the image also?.. please add details in the question. What is the expected least interval of successive pulses from the same sensor? \$\endgroup\$
    – User323693
    Aug 21, 2019 at 11:25
  • \$\begingroup\$ @Umar when triggered both S1 and S2 have 0V ie falling, when normal its 5volts \$\endgroup\$ Aug 21, 2019 at 12:09
  • \$\begingroup\$ I have added a timing diagram for you to edit to explain your problem. (1) Edit the timing diagram if there is a mistake in it. (2) Fix your capitalisation and punctuation. (3) Add some paragraph breaks. (4) Ask a question ending with a question mark (?). (5) You don't want to eliminate the debounce. You want to eliminate the bounce. \$\endgroup\$
    – Transistor
    Aug 21, 2019 at 12:21
  • \$\begingroup\$ @Transistor thank you, I can handle the debounce \$\endgroup\$ Aug 21, 2019 at 13:02
  • \$\begingroup\$ Please add the timing details. On time of both signals expected, off time expected.. and worst cases \$\endgroup\$
    – User323693
    Aug 21, 2019 at 13:27

2 Answers 2



simulate this circuit – Schematic created using CircuitLab

Figure 1. A possible solution using CMOS logic. ST = Schmitt trigger.

How it works:

  • In normal operation S1 sets the latch and S2 resets it.
  • If S2 doesn't arrive then C1 is charged up by R1. 1 s after Q goes high ST1 will go high triggering the buzzer.
  • A further second later ST2 will go high and reset the latch.
  • C1 will then discharge quickly through R3 (10 ms) turning off ST1 and then C2 will discharge through R4. The reset is now released and normal operation can resume.

I have shown all non-inverting logic for clarity. Check the sink capability of ST1 and 2 and adjust the values of R3 and 4 to limit the current to a safe value.

  • \$\begingroup\$ I have used SN74LS32 for OR gate, SN74LS279 for SR latch, HD74HC14P for Schmitt trigger and LM358 for buffer. Inverted S2 and output from OR gate for working with my inverting logic, it works, thank you \$\endgroup\$ Aug 23, 2019 at 23:14

Use S1 to Reset an SR latch and trigger a 555 monostable circuit.

The 555 one-shot will produce a negative pulse in response to the trigger. AND this with S2, and use it to Set the SR latch. The output of your latch is the error trigger.

This will malfunction if the S2 pulse ends after the monostable negative pulse, so you'd need to work the pulse-width into your design.

A better solution without that last weakness would take some extra logic -- perhaps using the 555 output as an !Enable input to another positive edge triggered device, triggered by S2, so the the rising edge of S2 cannot trigger.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.