In my VHDL design, I have a counter, and a reset mechanism. The counter counts up to 50M, and sets the "ready" signal to '1' and starts over. The reset signal is active high and resets the "ready" signal to '0' on a rising clock edge. Following is the VHDL code,
rst_pr : process(clk) begin if(rising_edge(clk)) then if(reset = '1') then ready <= '0'; end if; end if; end process; cntr : process(clk) begin if(rising_edge(clk)) then if(counter = 50e6) then ready <='1'; counter <= 0; else counter <= counter + 1; end if; end if; end process;
"ready" is a std_logic type signal. "counter" is an integer type signal. I also realize that "ready" signal can be multidriven at some point, i.e. the logic is broken. Following is the simulation code, also very simple (vivado)
rst_pr : process begin reset <='1'; wait for 50ns; reset <='0'; wait; end process; clkpr : process begin clk <='1'; wait for 5ns; clk <= '0'; wait for 5ns; end process;
Simulation shows "ready" is in the 'U' state all the time. This makes no sense, as at the beginning it is set to '0' by the reset process. I didn't share the entire code(entities,signal, library definitions etc.) to keep the post concise. Let me know if you want to see it.
Why does the simulator show "ready" as uninitialized?