I want to study the stability of my op-amp circuit with LTspice. I found this video as tutorial: tutorial on phase margin

I did the simulation with closed and open loop as suggested and got the following plots:

Closed loop: normal

And in open-loop as used in the video tutorial: open loop

How to read those plots and conclude if my circuit is stable or not?

0.3 V pulse response: pulse

Open loop chart with view of 0 dB point: enter image description here

  • 2
    \$\begingroup\$ Does the video explain and/or have you determined the gain and phase margins of the circuit? If not, there are plenty of tutorials and books which explain these. Without fully understanding gain and phase margin, doing a stability analysis is pointless. There is no stable / unstable. You determine the gain and/or phase margins and from that decide if that is good enough. I usually want a phase margin of 60 degrees or more. I also do a transient simulation to simulate an impulse response to confirm stability. \$\endgroup\$ Commented Aug 21, 2019 at 13:58
  • \$\begingroup\$ @Bimpelrekkie My last bode plot was 15 years ago. The tutorial explains how to obtain gain and phase margin in closed and open loop circuit to studay stability - but not define the stability criteria. From your expert criteria/point of view, do you think it's "stable"? \$\endgroup\$
    – Vinlar
    Commented Aug 21, 2019 at 14:13
  • \$\begingroup\$ Use the transient simulation mode to put a step in, and see what the output does. Does it overshoot or ring, is it deadbeat, or somewhere in between? Frankly, if you have the circuit modelled, then why analyse when you can simulate? Compare the step response of your model to the step response of the real circuit when you've built it, to check whether your model is sufficiently accurate. \$\endgroup\$
    – Neil_UK
    Commented Aug 21, 2019 at 14:47
  • \$\begingroup\$ For a stability check (phase and/or gain margin) you need also the phase response for the loop gain (open-loop analysis). \$\endgroup\$
    – LvW
    Commented Aug 21, 2019 at 14:55
  • \$\begingroup\$ OK I am adding transient responses for a 50Hz and 1kHz in the edit. More generally, any unity gain opamp circuit is stable? or it will still depend on input sensor capacitance? \$\endgroup\$
    – Vinlar
    Commented Aug 21, 2019 at 15:19

2 Answers 2


From https://payhip.com/b/5Srt ("Preview" button in the top right corner, chapter 1.5.1 on page 29):

"AC characteristic is a must. It says whether your design is stable, that is, no oscillations present when the feedback loop is closed. The easiest way to obtain the AC characteristic is to break the loop using a large inductor and to connect a large capacitor to the negative input as presented in Fig. 1.24:"

enter image description here

Typical AC characteristic plot with marked important points:

enter image description here

The opamp is stable if gain drops to 0 dB (the bandwidth in the above picture) while phase margin is above 0 degrees. In the above picture, the phase margin is almost 90 degrees for the gain equal to 0 dB (the bandwidth). In analog CMOS IC design, the rule of thumb is to design in such a way that the phase margin is at least 60 degrees.


I believe your plots are reversed. The top plot is the closed-loop response (but of the whole amplifier, including the input blocking cap). The second plot is the open-loop response -- and you should extend the frequency range to catch the point where the gain is 0dB, so you can see the phase at that point.

Note that this has been corrected -- see "Update 3", above.

You are looking for (and trying to avoid) the point where the open-loop gain is equal to exactly 1* -- this is the point in the second plot where the amplitude of the gain is 0dB (0dB = 1) and the phase is 0 degrees.

Your gain margin is the amount the gain would have to change at at 0 degrees of phase shift to get 0dB of gain (i.e., loop gain = 1). Your phase margin is the amount the phase would have to change at 0dB of amplitude gain to get 0 degrees of phase shift (again, loop gain = 1).

From the OP: "For 0db gain, phase is 41° (1.77MHz) and for phase 0°C, gain is -6.51 dB (3.16MHz)." This means that the phase margin is 41 degrees (which is a bit tight -- 60 degrees is generally considered safe for control systems involving mechanical parts) and 6.5dB (which is fine in almost anyone's book).

* Note that this whole "loop gain = 1" thing can get confusing, because in most control systems analysis, there's a summing junction in the loop that isn't taken into account in the analysis -- in that circumstance it's a "loop gain" of -1 that you're trying to avoid, not loop gain = 1.

  • \$\begingroup\$ For 0db gain, phase is 41° (1.77MHz) and for phase 0°C, gain is -6.51 dB (3.16MHz). I added a new plot in update 3 showing these points (and fixed labelling of plot 1 and plot 2 as you figured out) \$\endgroup\$
    – Vinlar
    Commented Aug 21, 2019 at 16:57
  • \$\begingroup\$ Is there a consensus on what to call loop gain? I have found books where loop gain is synonymous of loop transmission and as such it automagically takes care of the sign of the summing node, in that if there is a minus then loop gain is - A beta, while if there is a plus then loop gain is + A beta. Since the closed loop gain is given by A / (1 + A beta) in the former case, and by A / (1- A beta) in the latter, in both cases, with this notation, we must avoid loop gain = 1. (Sometimes I believe gremlins are in charge of choosing textbook notations.) \$\endgroup\$ Commented May 25, 2020 at 9:28
  • \$\begingroup\$ No, there isn't a consensus. Most books count the loop gain up to, but not including, the sign flip at the summing node (so \$H = G / (1 + G)\$). A significant minority do count that sign flip (so \$H = G / (1 - G)\$). I value consistency, but even so, while I usually use the former, there are times (usually when there's a sign flip in the process) where even though I'm swimming upstream against convention I use the latter. You just need to keep your eyes open. \$\endgroup\$
    – TimWescott
    Commented May 25, 2020 at 18:31

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