# Opamp circuit stability (LTSpice)

I want to study the stability of my opamp circuit with LTSpice, I found this video as tutorial: tutorial on phase margin

So, I did the simulation with closed and open loop as suggested and got the following plots:

And in open-loop as used in the video tutorial: How to read those plots and conclude if my circuit is stable or not?

Update 1:

removed (not relevant)

Update 2: 0.3v pulse response Update 3: Open loop chart with view of 0db point. • Does the video explain and/or have you determined the gain and phase margins of the circuit? If not, there are plenty of tutorials and books which explain these. Without fully understanding gain and phase margin, doing a stability analysis is pointless. There is no stable / unstable. You determine the gain and/or phase margins and from that decide if that is good enough. I usually want a phase margin of 60 degrees or more. I also do a transient simulation to simulate an impulse response to confirm stability. – Bimpelrekkie Aug 21 '19 at 13:58
• @Bimpelrekkie My last bode plot was 15 years ago. The tutorial explains how to obtain gain and phase margin in closed and open loop circuit to studay stability - but not define the stability criteria. From your expert criteria/point of view, do you think it's "stable"? – Vinlar Aug 21 '19 at 14:13
• Use the transient simulation mode to put a step in, and see what the output does. Does it overshoot or ring, is it deadbeat, or somewhere in between? Frankly, if you have the circuit modelled, then why analyse when you can simulate? Compare the step response of your model to the step response of the real circuit when you've built it, to check whether your model is sufficiently accurate. – Neil_UK Aug 21 '19 at 14:47
• For a stability check (phase and/or gain margin) you need also the phase response for the loop gain (open-loop analysis). – LvW Aug 21 '19 at 14:55
• OK I am adding transient responses for a 50Hz and 1kHz in the edit. More generally, any unity gain opamp circuit is stable? or it will still depend on input sensor capacitance? – Vinlar Aug 21 '19 at 15:19

I believe your plots are reversed. The top plot is the closed-loop response (but of the whole amplifier, including the input blocking cap). The second plot is the open-loop response -- and you should extend the frequency range to catch the point where the gain is 0dB, so you can see the phase at that point.

Note that this has been corrected -- see "Update 3", above.

You are looking for (and trying to avoid) the point where the open-loop gain is equal to exactly 1* -- this is the point in the second plot where the amplitude of the gain is 0dB (0dB = 1) and the phase is 0 degrees.

Your gain margin is the amount the gain would have to change at at 0 degrees of phase shift to get 0dB of gain (i.e., loop gain = 1). Your phase margin is the amount the phase would have to change at 0dB of amplitude gain to get 0 degrees of phase shift (again, loop gain = 1).

From the OP: "For 0db gain, phase is 41° (1.77MHz) and for phase 0°C, gain is -6.51 dB (3.16MHz)." This means that the phase margin is 41 degrees (which is a bit tight -- 60 degrees is generally considered safe for control systems involving mechanical parts) and 6.5dB (which is fine in almost anyone's book).

* Note that this whole "loop gain = 1" thing can get confusing, because in most control systems analysis, there's a summing junction in the loop that isn't taken into account in the analysis -- in that circumstance it's a "loop gain" of -1 that you're trying to avoid, not loop gain = 1.

• For 0db gain, phase is 41° (1.77MHz) and for phase 0°C, gain is -6.51 dB (3.16MHz). I added a new plot in update 3 showing these points (and fixed labelling of plot 1 and plot 2 as you figured out) – Vinlar Aug 21 '19 at 16:57