Tl; Dr; I make a lot of reads to a RAM, physically incrementing the address and get more errors every time i restart the read process on address 0x0. Is this the Row-Hammer ?
I made a question regarding RAM problems, it's still the same PCB and i found that with only reads the errors increment.
This picture is from a custom software which reads data and compares the read data to zero. The numbers in the third column are the number of bits which are not zeros from the read data.
What I can say is, that the first 60MBytes are error free and then the errors start.
I changed the ref voltage IC for DDR3 (running with 1.5V and Vtt 0.75) with an IC where no errors occured - no improvement.
Also, the errors are single bits and it can happen that a bit swaps back to zero and another in the same row changes to one.
I am using a RAM from Alliance Memory.
How can I determine if this is a Row hammer problem or not? What can I do against it.
I read here that one prevention mechanism would be increasing the refresh rate and/or to make sure that access to the same addresses should happen slower than the refresh rate, is this valid?
EDIT 1: Additional info to the routing
The exact part number of the RAM is AS4C256M16D3B-12BCN - Commercial temperature. From my measurements the RAM doesn't reach a temperature above 50°C. Measured on the chassis of the RAM.
I tried various settings in the Uniphy IP Core (CAS settings and so on): From using ODT (Can't use dyn ODT because the Cyclone V FPGA is not able to use read leveling) to increasing CAS latency, to modifiying memory timing. I made a SI simulation, but wasn't able to eliminate the errors with adjusting slew rates tds, tdh, tlh and dls.
My current setting is, from the RAM side seen:
CAS latency : 5
Output drive strength : 40 Ohms impedance
No additive CAS
The measurement of the 1.5V supply of the RAM showed the following:
Tripple: can't tell from the osci, but the step down converter runs at 700Khz.
The layout of the RAM is:
The red lines are bottom and the blueish ones are on top. Ram is on the Top, decoupling capacitators and RZQ resistor is on the bottom.