Tl; Dr; I make a lot of reads to a RAM, physically incrementing the address and get more errors every time i restart the read process on address 0x0. Is this the Row-Hammer ?

I made a question regarding RAM problems, it's still the same PCB and i found that with only reads the errors increment.

This picture is from a custom software which reads data and compares the read data to zero. The numbers in the third column are the number of bits which are not zeros from the read data.

enter image description here

What I can say is, that the first 60MBytes are error free and then the errors start.

I changed the ref voltage IC for DDR3 (running with 1.5V and Vtt 0.75) with an IC where no errors occured - no improvement.

Also, the errors are single bits and it can happen that a bit swaps back to zero and another in the same row changes to one.

enter image description here

I am using a RAM from Alliance Memory.

How can I determine if this is a Row hammer problem or not? What can I do against it.

I read here that one prevention mechanism would be increasing the refresh rate and/or to make sure that access to the same addresses should happen slower than the refresh rate, is this valid?

EDIT 1: Additional info to the routing

The exact part number of the RAM is AS4C256M16D3B-12BCN - Commercial temperature. From my measurements the RAM doesn't reach a temperature above 50°C. Measured on the chassis of the RAM.

I tried various settings in the Uniphy IP Core (CAS settings and so on): From using ODT (Can't use dyn ODT because the Cyclone V FPGA is not able to use read leveling) to increasing CAS latency, to modifiying memory timing. I made a SI simulation, but wasn't able to eliminate the errors with adjusting slew rates tds, tdh, tlh and dls.

My current setting is, from the RAM side seen:

CAS latency : 5

Output drive strength : 40 Ohms impedance

No additive CAS

And memory Timing

The measurement of the 1.5V supply of the RAM showed the following:

Ueff: 1.54V

Uripple: 400mV

Tripple: can't tell from the osci, but the step down converter runs at 700Khz.

The layout of the RAM is:

The red lines are bottom and the blueish ones are on top. Ram is on the Top, decoupling capacitators and RZQ resistor is on the bottom.

enter image description here

  • 3
    \$\begingroup\$ What exact part number it is, what is the clock frequency and CAS latency setting you are using? And also any other useful info I forgot to ask, such as PCB layout, bypass capacitor value and placement and ripple of supply voltage? \$\endgroup\$
    – Justme
    Aug 22, 2019 at 16:34
  • \$\begingroup\$ I added the information in the question under edit 1 \$\endgroup\$
    – Eggi
    Aug 23, 2019 at 6:16
  • 3
    \$\begingroup\$ Just to be sure, you said 400mV ripple, right? It can't work if supply is 1.5V with 0.4V ripple. Also the rererence ripple needs to be below 15mV. How do you generate the Vref? \$\endgroup\$
    – Justme
    Aug 23, 2019 at 10:21
  • \$\begingroup\$ The ref. voltage is generated with a TPS51100 routed and component placement is as in the reference design. I'll try to add come cap. to decrease the ripple. \$\endgroup\$
    – Eggi
    Aug 26, 2019 at 10:25
  • \$\begingroup\$ So, eliminated the ripple <15mV on both VTT and Vref. The error still happens. I have seen that removing the 100nF cap on the RAM side at Vref decreases the errors. Can this be an ESR fault? \$\endgroup\$
    – Eggi
    Aug 28, 2019 at 7:18


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