Let me write the steps of ADD B, as I've understood it till now.


  • ALE goes high
  • Memory location(say \$2000_h\$) is taken from Program Counter to Memory Address Register(which points to the passed location), via \$\small{A_{15}}\$-\$\small{A_8}\$ and \$\small{AD_7}\$ - \$\small{AD_0}\,\,\$(which will be latched)
  • ALE goes low.


  • \$\small{\overline{MEMR}}\,\$ is generated, the contents in \$2000_h\$ \$^ \dagger\$ is passed to the Instruction Decoder.

T2 and T3:

  • I really can't understand these two states, I can see that the \$\small{\overline{MEMR}}\,\$ signal goes low in T2 and its stated tht the addition is done in T3, but the ALU will have evaluated the sum, once the temporary register is set, is the temporary register set only on the T3?

\$^\dagger\$ I could see that different instructions' OPCODE is divided differently, for example, for ADD B, the first 5 bits correspond to ADD and the next three bits correspond to the desired register, but for an instruction like MOV B,C the first two bits corresponds to the MOV and the next 6 correspond to the registers. How are OPCODES actually read correctly? Because, if it was constant that the first 5 bits always correspond to the instruction, then it can be understood easily, but that's not the case.

Finally, can someone please list out the steps in terms of Time-States for the instruction ADD B.

Program Counter is incremented somewhere along the way, but I don't know where that is happening.

In Ben Eater's 8 bit computer, there is a separate T-state for PC increment, but 8085 is far more advanced I suppose.

  • \$\begingroup\$ Why do you need this information? \$\endgroup\$ Commented Aug 23, 2019 at 6:54
  • \$\begingroup\$ @BruceAbbott I don't know, I'm currently learning about 8085 and interfacing it with other IC's. I just don't understand the last two T-States. \$\endgroup\$ Commented Aug 23, 2019 at 6:57

1 Answer 1


it's late here and I may only help a little. But "ADD B" is a T4 type instruction, as you probably know. It also has been many years since I did anything with the 8085A and I apologize for any mistakes in advance. But here goes regarding the four T states of the "ADD B." (I'm just looking at the datasheet right now to refresh some of my memory.) Note that each T state shown below will have either an 0 or 1 to indicate falling-edge or rising-edge of the clock. (A T state begins with the falling edge.):

T1-0: \$ALE=1\$; \$S_0=1\$; \$S_1=1\$; \$IO/\overline{M}=0\$; \$\overline{RD}=1\$; \$\overline{WR}=1\$; Latch \$PC\$ to \$MAR\$ (which appears on \$A_{15}..A_0\$); Actively drive \$MAR\$.

T1-1: \$ALE=0\$

T2-0: Start PC increment; \$\overline{RD}=0\$; Float \$MARL\$ (\$AD_7..AD_0\$) to allow external circuitry access

T2-1: Continue PC increment (external circuitry may start to provide data on \$AD_7..AD_0\$)

T3-0: Instruction byte stabilizing on \$AD_7..AD_0\$

T3-1: Latch \$MDR\$ from \$AD_7..AD_0\$ and enable \$MDR\$ output on internal bus

T4-0: Address Bus Idle; Latch \$IR\$ from \$MDR\$ and start decoding of \$IR\$

T4-1: Address Bus Idle; Decide if two more states are required for the instruction.

That's the official details and just describes the bus cycle from an external view.

Internally, things are different. The ADD B instruction would need to set up the ALU opcode value and would require addressing the register file to read the B register onto the internal bus and then into the ALU's temp register (it's other register is the accumulator.) That temp register value would then be present at one of the ALU inputs and at some point the ALU output now present on the temporary bus would be stable long enough to start the write-back process into the accumulator latch. All this before the next instruction's byte would need to use the internal bus in order to transfer the MDR latch value into the IR latch.

But the essence of T2 and T3 is to allow the external memory system to respond to the request for an instruction byte and to get that byte value into the 8085A. T4 is for decode and determination if the instruction requires more states (or not.) Though, keep in mind that T1 and perhaps T2 of the following instruction cycle might also be used to complete the prior instruction after decoding (if it doesn't require any added bus operations, such as read/write.)

  • \$\begingroup\$ Thank you very much for answering, I'm very new to digital electronics, so please bare with my naivety here; what do you mean by "set up ALU opcode value"? When is the B register addressed and the contents are transferred to the temp reg? This is the final step right? as the ALU constantly calculates the sum of the two(does it, that is why we have a buffer right?) What does MDR basically do? \$\endgroup\$ Commented Aug 23, 2019 at 9:36
  • \$\begingroup\$ @Aravindh The ALU will have its own opcode to tell it to add or subtract or perform some logical operation. Decoding the instruction will work that out as part of the decoding process. Sure, the ALU can continually perform, but you cannot always allow its output to drive the internal bus which may be in use for some other reason. The MDR is the "memory data register." \$\endgroup\$
    – jonk
    Commented Aug 23, 2019 at 9:43
  • \$\begingroup\$ Yeah I get that the ALU cannot keep on putting values on the bus,I meant, that's the reason why we put a buffer in-between the bus and the ALU, right? When is the B register value transferred to the temporary register? One more question: What do you mean by "decide", what is the internal process of deciding? I mean, if it had to take more T-states, how will it "decide" and what does "Float MARL" mean? \$\endgroup\$ Commented Aug 23, 2019 at 9:50
  • \$\begingroup\$ @AravindhVasu The B register has to be addressed (it's in a register file with more than one register.) How exactly that works is a detail left to the designers. But it must be done, somehow. That addressed value will have to pass through a tri-state buffer to the bus, which has to be enabled. Then the temp register has to latch that bus value. The decoding process sets all this up with, often, a state machine and control line outputs derived from that. Most of the complicating details are swept under the "decoder and state machine" rug. The rest always looks clean and easy. \$\endgroup\$
    – jonk
    Commented Aug 23, 2019 at 20:14

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