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I've seen various answers regarding routing of decaps, wondering which method is optimum for better power distribution and noise immunity:

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Another question is, will this routing cause ground loops? I usually don't share ground vias but in this case, I need a bigger ground plane on the top layer:

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Edit: This is an 8 layer board with dedicated GND and PGND ground planes.

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  • \$\begingroup\$ you will always have ground loops and thus have some interaction; its your job to understand what layout methods (and possibly adding extra capacitors and series VDD resistors, to create local-batteries) are needed to achieve the Bit Error Rate of your datalink, or the Deterministic Jitter of crucial signals, or the Code Spread from your AnalogDigitalConverter output codes, you need to achieve satisfactory system behavior. \$\endgroup\$ – analogsystemsrf Aug 25 '19 at 4:51
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Most of this only becomes critical in 2 categories:

  • High precision, e.g. measuring micro volts
  • High speed, e.g. 100+MHz signals

You need to start thinking of your signal paths in loops, there is your signal, and also its return path, either through a power supply, ground, or some other signal line for differential signals.

You want this return path to follow your signal as closely as possible, be it next to it on the same layer, or directly under it on the opposite side, this couples each signals electric and magnetic feild to the other and both reduces outwards radiation, but also reduces how well external signals can couple, this is sometimes called "Loop area"

The sharing via's / grounds is only an issue when the current from one source can introduce a large enough voltage shift to upset another source, for high speed, the inductance of the via can make it drop a significant voltage, and for precision, a few mA can introduce more noise than signal to sensitive circuits,

For your via placement, the rule of thumb is your device connects to its decoupling capacitor, and then to the power rail, and you care more that the traces to the decoupling are short vs the traces off to your power supplies. this acts as a weak filter, as the resistance and more so the inductance of the traces form a low pass filter to soak up either supply noise in, or noise from your device out to the supply.

for high speed signals, vias are quite inductive, where possibly it is generally preferred that the decoupling is on the same side as the chip, and them the connection to the power rail jump off to the other side of the board.

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  • \$\begingroup\$ I would say you missed a critical category; switch mode power supplies. Decouplng and ground routing is critical in these as there is significant switching noise that must be managed. \$\endgroup\$ – Peter Smith Aug 24 '19 at 11:54
  • \$\begingroup\$ They would fall under high speed, when they start switching fast enough it falls under the same issue of inductance, as to switching noise, if you plan out both the signal and return path of each part you end up with the same effect, a reduced loop area, \$\endgroup\$ – Reroute Aug 24 '19 at 12:02
  • \$\begingroup\$ Forgot to mention that I have a dedicated PGND and GND layers, will this help? I usually don't share ground vias between components but I have a very limited space. This design is a motherboard with a 200MHz MCU and 100kHz ~ 2.5MHz DC-DC converter. \$\endgroup\$ – cknz Aug 24 '19 at 12:29
  • \$\begingroup\$ I do not have your schematic on hand, so you will have to answer that part yourself, or provide enough information for me to, does the current / current spike from one node that is sharing the via create a significant voltage, e.g. more than 10mV, if so then it may be an issue. Every time you approach a part of a circuit you end up laying it out a different way, when I get stuck optimizing something I generally duplicate its group of components off the board, optimize it there, and then work it back into the PCB \$\endgroup\$ – Reroute Aug 24 '19 at 12:39

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