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I do not understand the precise role of the sensitivity list in a process in VHDL.

For instance, consider an architecture with 3 input signals: a, b, c.

I read that if we write: PROCESS (a, b)

we get that the process is activated by any variation of a and b. Now I have 2 doubts:

1) What does the sentence "a process is activated" mean? A process is a hardware component, like a flip flop. I do not understand the meaning of "activation".

2) If we write inside the process something like: "if c = '1' then ...", the process will depend also on c, although we have inserted only a and b in its sensitivity list. What is the difference? Does it determine a different hardware synthesis?

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3 Answers 3

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The process sensitivity list is primarily a hint to a simulator. It only triggers an evaluation of (i.e., "activates") the process when an event occurs on any signal that's listed there.

It does NOT affect synthesis at all, to my knowledge. Synthesis is based entirely on the behavior described inside the process block.

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  • \$\begingroup\$ With "triggers" do you mean that inside the process, an event that occurs on listed signals will determine a variation of other signals? \$\endgroup\$
    – Kinka-Byo
    Aug 24, 2019 at 14:43
  • \$\begingroup\$ Yes. In a simulator, a process is represented by a snippet of computer code. That code is executed whenever a listed event occurs. When that code executes, it creates new events on the signals that get assigned values in the process body. \$\endgroup\$
    – Dave Tweed
    Aug 24, 2019 at 14:48
  • \$\begingroup\$ Without a sensitivity list, the process requires a wait statement, for synthesis as well. \$\endgroup\$ May 23 at 16:57
  • \$\begingroup\$ @SimonRichter: Do you have any evidence for that? See also Mitu Raj's answer. \$\endgroup\$
    – Dave Tweed
    May 24 at 11:35
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In VHDL, sensitivity list is ignored while synthesis. The hardware synthesised depends only on how you described it inside the process block. You can confirm this by running post-synthesis functional simulation with and without sensitivity lists. You will get the same functionality.

However, it is essential to include correct senstivity list while doing behavioral simulation of RTL, otherwise you may get something called 'Synthesis and Simulation Mismatch'. i.e., what you are simulating will be different from the actual functionality you are going to get from the hardware after synthesis. Which then defeats the purpose of simulation.

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As Dave Tweed has indicated, the sensitivity list tells the simulator when to execute the code in the process. The process is executed once on startup then executed again whenever there is an event on one of the signals in the sensitivity list. A helpful way to think about it is that the block of code:

process (a, b)
begin
   -- (Bunch of code goes here)
end process;

is exactly equivalent to this other block of code:

process
begin
   -- (Same bunch of code as above)
   wait until a'event or b'event;
end process;

(And remember that a VHDL process is always an infinite loop.)

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  • \$\begingroup\$ But I thought that a process was simply the representation of an hardware block. So what does "process execution" mean? It looks like "a flip flop execution", it is a circuit... so something that is always active. I do not understand it. \$\endgroup\$
    – Kinka-Byo
    Aug 24, 2019 at 19:39
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    \$\begingroup\$ No that's not what a process is. Remember that VHDL was created to describe hardware for simulation purposes. Synthesis was added later on, and as a result there are a ton of things that are perfectly valid code but cannot be synthesized. For example, you could have a process block that contains multiple wait statements, one after the other. This probably could not be synthesized but it's perfectly legal VHDL. \$\endgroup\$
    – Mr. Snrub
    Aug 24, 2019 at 21:22
  • \$\begingroup\$ Ok ok thank you. And what does it happen if I put a "wrong" signal in the sensitivity list? With "wrong" signal I mean a signal whose variation does not change other signals' values inside that process. \$\endgroup\$
    – Kinka-Byo
    Aug 25, 2019 at 11:49
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    \$\begingroup\$ Here's another way to think about it. The statement process (clk, rst) tells the simulator that "this process only updates things whenever the clk or rst signal changes". If you omit a signal from the sensitivity list, then the simulation will no longer react to changes in that signal. But, confusingly, the synthesizer would probably still get it right. \$\endgroup\$
    – Mr. Snrub
    Aug 25, 2019 at 19:19

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