I am learning Verilog and using Icarus Verilog for compilation and simulation. Is it possible to visualizate result somehow as a schematic, RTL etc?
Unfortunately Icarus doesn’t seem to have an up-to-date synthesis flow, which you would need to visualize your RTL as logic.
You could try the free online evaluation versions of Xilinx Vivado. This will extract a post-synthesis schematic showing how compilation and synthesis rendered your RTL into internal logic elements (LUTs, flip-flops, i/o blocks, etc.) It has a simulator (XSIM) as well.