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I wonder how fast I can read from a DDR SDRAM (known as DDR1) clocked at 200MHz. The controller will be implemeted on an FPGA.

I have 8 bit data interface to the DDR. Each data pin reached 400Mbps. Therefore the total throughput is 3.2Gbps = 400MBps. However there will be an overhead for read commands to the DDR.

Including those what is the practical maximum READ throughput I can reach?

Regards

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  • \$\begingroup\$ for the practical maximum, you would need to sit down and work through your latency contributions, e.g. refresh cycles, row and column latency, etc, all of these chip away at your maximums, \$\endgroup\$ – Reroute Aug 25 '19 at 12:55
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If your DDR SDRAM has multiple banks, it is often possible to interleave the bank burst transfers in such a way that all of the other overhead is "hidden". And if you're accessing memory sequentially anyway, you can sometimes even forget about separate refresh cycles. This means that you can sustain the raw (peak) bandwidth of the data bus more or less indefinitely.

I work with high-bandwidth video systems, and we do this sort of thing all the time, for external frame buffers attached to FPGAs.

Implementing a DDR SDRAM controller that's sophisticated enough to interleave bank accesses is rather tricky — we nearly always use the FPGA vendor's IP for the physical memory controller, and then add our own multi-port access multiplexer on top of that.

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