which is the physical cause of hold time of a D flip flop? Why is it necessary to keep its input data constant for a certain amount of time?
In addition to @Bimpelrekkie's answer, you should know that the clock signal may be buffered and inverted inside the flip-flop. So there are internal clock signals that may not be in their final stable states at the instant that the external clock rises. The "hold" time ensures that the input data remains valid until all of the internal clock signals have become stable.
Clocked logic elements are built from pairs of latches. We’ll call them Stage 1 and Stage 2. (Often they’re called master and slave, but I dislike those terms and avoid them when I can.)
A basic clocked flop works like this:
- Stage 1 latch passes input during clock-low time and holds during clock high
- Stage 2 latch passes input during clock-high time and holds during clock low
You may recall that latches work by selecting between the input and self-reinforcing feedback. To reliably catch and hold the input, the Stage 1 latch input state has to be stable long enough so that the feedback state is settled when the Stage 1 latch closes and Stage 2 opens. Setup time is the maximum of this feedback delay, hold time is the minimum.
To keep things simple most logic designers try to set up the relative max/min delays for clock and data to ensure zero hold time, but this isn’t always the case. Sometimes hold will be after the clock, sometimes before, depending on the delays of clock and data to the flop.
All circuits have delays due to (parasitic) capacitances which need to be (dis)charged. The (dis)charging is done through switches (usually transistors) which do not have a zero series resistance. This means that the speed of any change is limited by at least some RC timing constant.
The hold time is needed because the flip flop isn't infinitely fast. It needs some time to settle in the desired state. If you know a circuit or component that is infinitely fast then please let me know!
The hold time needed for most of the will be mentioned as 0 seconds. It doesn't mean the devices are infinitesimally faster but they have logics which doesn't need the data to be stable after clock edge.
Another example is hold time mentioned in negative seconds, There, the data need not be stable during clock transition. Anyone can supply examples for these cases too.
Propogation delay, rise time , assymetrical sub sections and temperature effects demands the input signal to be stable for certain duration so that system can reliably sample the data (see the stable data). Finally, follow the specifications in the datasheet from the supplier.
One additional issue: If the data is in the "illegal" voltage range between "high" and "low" when the clock changes you will experience meta-stable behaviour; see its Wikipedia entry.
The cause is the capacitances that creates RC time constants within the FF.
This capacitance is usually from the gate or base of transistors to somewhere else in the circuit, but also to a lesser extent, in wiring, packaging, etc. The capacitances that create hold time requirements can be in multiple places. It can be in the clock buffers, perhaps delaying the clock to state holding circuits. Or it can be in transistors preventing or enabling feedback to hold the state. Or in a state holding pair.
If the input changes before the clock can enable state holding via feedback, both of which (clock path and hold buffers) have finite rise/fall times due to intrinsic capacitance, then any input change before the end of the hold time can corrupt the state that the clock edge is trying to establish before it can be established. Perhaps by partially charging or discharging a capacitance below the threshold need for reliable feedback establishment to hold the state indefinitely.
The hold time will vary with the design of the circuits in the clock, input, and state holding circuitry, as well as component characteristics and their variation (via manufacturing, temperature, aging, etc.)