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I'm studying CMOS op-amps. At the very beginning of the chapter, the author of my book says:

"obtaining low output impedance can be problematic. Nevertheless, the typical use that we make of op-amps in integrated systems does not lead to a strict request for low output impedance. Even better, in some cases the output impedance may not be a problem at all."

To prove it, he proposes the following example:

enter image description here

He finds the following expressions:

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He then says:

"Since 1/gm is much smaller than r0, the time behaviour of the output voltage is mainly controlled by the transconductance gain and is almost independent of the output resistance. [...] When the feedback network comprises only capacitors (and switches) the output resistance is not relevant. We can use a special class of operational amplifiers where the output resistance can be very high and, possibly, used to enhance the voltage gain. This class of operational amplifiers is called OTA (operational transconductance amplifier)."

Question 1: why does the author model the op-amp with a transconductance generator gm*vi having in parallel the output resistance r0? The model of an op-amp should be the following:

enter image description here

Question 2: I'm able to find expressions 5.3 and 5.4: the charge on C1 (i.e. Q1=C1*vin) is shared with the series connection C-C0. But why does the charge on C1 distribute only on the series connection C-C0? Actually this charge has also two paths toward ground through which it can flow: r0 and the voltage-controlled current source.

Question 3: I'm not able to find expressions 5.5, 5.6 and 5.7. Can you give me some hints?

Question 4: the author says that it is an OTA, whose working principle is based on a very large value of the output resistor. But why does he talk about OTA if the chapter is dedicated to op-amps?

Thank you

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  • \$\begingroup\$ I've used the standard CMOS opamp topology, with diffpair, and two paths for the diffpair outpur currents to wrap around to create opposing PULLUP and PULLDOWN currents, in several ways. One was 100MegOhm resistor equivalent, in a PLL lock detector; the opamp produced 10 nanoamps Iout per Volt of input difference; this was a bad opamp, but a great OTA and a fantastic (very small) 100,000,000 ohm resistor. \$\endgroup\$ – analogsystemsrf Aug 27 at 12:17
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  1. Remember this is a CMOS op amp you are dealing with, so internally it would look like this, you could relate that trans-conductance to that transistor that is right at the output so any output impedance would become parallel to it. This is a model issue so it does not have to be gm per se, but it is a reasonable way to do it generally.

    schematic of op-amp

  2. The time is 0+ so for that condition you would consider the capacitor(if it is not charged) to be smaller impedance than the resistance(akin to a close circuit) so most of the current would go towards the capacitor at that instant. Your assumption is correct, but the component that goes to ro would be very small.

  3. Time is infinite so just consider the circuit stable and do each loop following KVL, for Vo ignore the current Co, for Vi it is a bit trickier just think of it like this you got Vi applied to C1 and that goes to ground. C follows what you told us in question 2 and finally do a voltage divider to figure out the relation between Vo and Vi. You need 5.6 to get 5.5 so the order is kinda messed up I would say.

schematic

simulate this circuit – Schematic created using CircuitLab

  1. OTA is a special type of op-amp, it uses diodes on the differential inputs to generate a large resistance on the input. Here is the datasheet for one so you get to know it better. ----> Datasheet
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  • \$\begingroup\$ Thank you for your answer. I still have problems with those equations. Since time is infinite I consider all capacitors as open circuits. In this way I find Vo, but then I don't know how to find Vi. Should I perform a time domain analysis? This would lead to differential equations... \$\endgroup\$ – Stefanino Aug 28 at 21:05
  • \$\begingroup\$ I would do a frequency domain analysis turn all capacitors into impedances 1/wc and when you do the voltage divider to get Vi all the frequencies will cancel out, for the time constant at the end you need to do a time analysis though. \$\endgroup\$ – Juan Aug 29 at 1:21

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