Reducing EMC from a long trace where one end is normally floating

Following on from this question about a PCB layout with EMC issues, I'm currently reworking the design to minimise breaks in the ground plane and try and identify any other EMC issues.

One thing that caught my eye was a relatively long (40mm) 5V trace that runs across the board. This trace runs to a connector that is used for debugging and is there to allow the board to be conveniently powered from the debug connector, without the need to wire in the main power supply. However, during normal operation, this ends up being an unterminated trace that is connected to the SMPS 5V, and is probably acting as an antenna, radiating switching noise and possible picking up the GSM signal and injecting it back into the board.

One simple solution is to simply not have that trace at all and require the board be externally powered during programming. However, this got me thinking: in situations where removing the trace may not be practical, how would you go about eliminating the negative EMC effects caused by traces like that, which are normally left disconnected?

• Impedance match with parallel resistor to ground. Change the trace so it has characteristic impedance such that the resistor doesn’t draw too much current. But seriously, don’t leave large floating traces. – user110971 Aug 26 '19 at 9:13
• An RC termination to ground as close as possible to the end of the net is where I would start. Set a cutoff frequency a bit above the SMPS loop crossover frequency (perhaps an octave). – Peter Smith Aug 26 '19 at 10:13
• @user110971 thanks for your comment. My understanding of what you've said is as follows: calculate/measure the impedance of the trace (I guess calculating using the trace thickness and geometry is simpler) and then place a similar valued resistor at the end to ground. This is to allow maximum transfer of the RF power to the resistor, thus preventing any reflections from flowing back up the trace and into the rest of the circuit. I guess in this case, though I need to actually know the frequency of the noise involved. Is that correct? – Inquisitive Engineer Sep 9 '19 at 11:45
• @InquisitiveEngineer I did turn my comment into an answer, so you can read that for more details. In short, yes. However you do not need to know the frequency of the noise. The resistor has the same value for all frequencies of interest. The reason for doing that is to prevent reflections, but not because it will feed back to the source. It’s to prevent the trace from resonating, thus becoming an antenna. See the last figure in my answer below. At the quarter wavelength, 3/4 wavelength etc. the track resonates and becomes a very good antenna. If you impedance match it, you can prevent this. – user110971 Sep 9 '19 at 11:53
• @InquisitiveEngineer the characteristic impedance of the track will be relatively constant for the frequencies of interest. – user110971 Sep 11 '19 at 19:57

I wasn’t going to answer this question initially, but it seems nobody else has given an answer. There are three main things that I see on that PCB that are problematic. Firstly, you need to ensure that you have a solid reference plane below all of your traces. Secondly, you need to avoid having so many jumps on your sensitive traces. Finally, you need to impedance match your high frequency and floating traces.

As you know current travels in loops. To minimize the radiation from a current loop you need to decrease the loop area. It all comes down to Faraday’s law:

$$\oint_\mathcal{\partial S} \mathbf{E} \cdot \mathrm{d}\mathbf{s} = -\dfrac{\mathrm{d}\Phi_B}{\mathrm{d}t}.$$

So the larger the loop area, the greater the rate of change of the magnetic flux. The return current on the ground plane follows the PCB track very closely for the frequencies we are interested in. Here is a simulation of the current density on a ground plane:

source

So to minimize the current loop area you need to ensure there is an uninterrupted reference plane below or above you track. If there is a gap, the return current will need to make a detour, increasing the loop area.

When you jump to a different layer through a via, the reference plane can change. The reference plane that is used is the one that minimizes the current loop area, because it has the lowest impedance. However if you change layers, this can happen:

source

The path of least impedance for the return current is plane 1 until you reach the via. Then it becomes plane 2, but the return current cannot simply jump between the two planes. It will go from plane 1 to the nearest capacitor between plane 1 and plane 2. This can increase the loop area significantly and, since the nearest capacitor is probably a decoupling capacitor, introduce noise in a sensitive part of your board. To prevent all of that avoid changing layers on your high speed and long traces. If you have to change layers, place a small capacitor between the reference planes as close to the via as possible.

If you have a track that is not impedance matched, it can become an accidental antenna. Any high frequency signal on the track, either induced from external sources or directly driven by the source, can bounce between the source and the load for a long time radiating emissions. The antenna efficiency of an open circuit track has the following characteristic:

source: page 24

For reference, the antenna efficiency of a matched track is -40 dB at all frequencies. You can see that at some frequencies your tracks can become very good antennas. It is not enough to simply ground the tracks at one end. Quarter of a wavelength away your short circuit become an open circuit. If you want to use this strategy, you need to ground the track repeatedly at a suitable interval (at least $$\\lambda / 10\$$). It is much more practical to impedance match your tracks, reducing your worst case emissions by a factor of 10000.

• I'm trying to understand the GROUND CURRENT FLOW drawing you placed. Is the image on the left describing 3 layers (top signal, reference plane, bottom signal)? I'm trying to see how this applies to my case, which is a 2-layer PCB. – Inquisitive Engineer Sep 9 '19 at 11:57
• @InquisitiveEngineer Yes. The image demonstrates the problem of having to change reference plane. The image on the left shows that there is no problem, if you have the same reference plane. Maybe in a stack up like this: signal, ground, signal, signal. Having two signal layers with the same reference plane has its own problems though. – user110971 Sep 9 '19 at 12:02
• @InquisitiveEngineer how it relates to your problem is that you should be using a 4 layer board. GSM is in the high MHz low GHZ range. Especially because you are cutting you ground plane and introducing discontinuities. The return current then needs to go around. See all the traces on the left side of the IC in the middle. They cross a ground discontinuity. – user110971 Sep 9 '19 at 12:06
• You're right - I didn't pay attention when routing those signals underneath the microcontroller IC in the middle. 4 layers would definitely make it much better. As a learning exercise, I've re-routed the board, still using 2 layers, but significantly reducing the number and length of traces on the bottom layer. I'm hoping to get a prototype made and compare the difference in EMC. I might also do a 4-layer version and compare that as well. – Inquisitive Engineer Sep 11 '19 at 19:45
• I see what you mean regarding the return current needing to change planes. I understand that this is important is any PCB where the signal cross more than one plane (so this would be true for a 4 layer board S-P-P-S). I can see how adding a small value decoupling capacitor between the planes close to the via allows the return current to jump planes. Or ideally, as you said, minimise changing layer on critical traces. – Inquisitive Engineer Sep 11 '19 at 19:50