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I have this Boolean equation

B'*C'*D' + A*C*D + C*D*E'

and I was just wondering how to use nand gates to express this equation.

With the schematic the inputs are

NAND1 it is B'*C'*D'

NAND 2 it is A*C*D

NAND 3 it is C*D*E'

This schematic shows me converting the first AND inputs to NAND then the OR to NAND and I was trying to build a circuit with this logic.

schematic

simulate this circuit – Schematic created using CircuitLab

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    \$\begingroup\$ Do you know DeMorgan's Theorem? \$\endgroup\$ Commented Aug 26, 2019 at 14:34
  • \$\begingroup\$ Yes, I understand the basics and that why for the OR gate put the three inputs into the one NAND (10) gate. That being said would it be the same if i remove nand 4 to 9 as I am doing a double inversion? \$\endgroup\$
    – FZRAM
    Commented Aug 26, 2019 at 14:43
  • \$\begingroup\$ NAND4-9 serve no logic function in your circuit. All they do is add delay. \$\endgroup\$
    – brhans
    Commented Aug 26, 2019 at 15:02
  • \$\begingroup\$ You assert that the input to NAND1 is B'C'D', but i assume that the actual inputs to your system are B, C, D. So you need to invert each of those individually before feeding them to NAND1. Similarly for the inputs to NAND2 & 3 where appropriate. \$\endgroup\$
    – brhans
    Commented Aug 26, 2019 at 15:05
  • \$\begingroup\$ Three inverters in series may be replaced by one only. So the chain of NAND1, NAND4 and NAND7 may be replaced by NAND1 only, the same is true with the chains starting with NAND2 and NAND3. \$\endgroup\$
    – Uwe
    Commented Aug 26, 2019 at 15:18

1 Answer 1

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Its just and application of Demorgan's theorem.of Demorgans theorem. The whole problem can be solved using repeated application of three equations.

  1. NOT(A) = NAND(A,A,A)

  2. AND(A, B, C) = NOT( NAND(A,B,C) )

    AND(A, B, C) = NAND( NAND(A,B,C), NAND(A,B,C) , NAND(A,B,C) )

  3. OR(A,B,C) = NOT( NAND(NOT(A), NOT(B), NOT(C) )

So...

B' = NAND(B,B,B)
C' = NAND(C,C,C)
D' = NAND(D,D,D)
X = NAND(B',C',D')
B'C'D' = NAND(X,X,X)

Y = NAND(A,C,D)
ACD = NAND(Y,Y,Y)

E' = NAND(E,E,E)
Z = NAND(C,D,E')
CDE' = NAND(Z,Z,Z)

T = NAND(B'C'D', B'C'D', B'C'D')
U = NAND(ACD, ACD, ACD)
V = NAND(CDE', CDE', CDE')
W = NAND(T,U,V)
B'C'D' + ACD + CDE' = NAND(W,W,W)

Without any optimization it would be 15 3-input NAND gates.

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