I'm using a Si53342-B-GM
as a clock buffer.
In some cases I only need to distribute a single clock signal and in some of my cases I only have a single ended input signal.
While the data sheet describes every detail in dealing with single ended input signals it doesn't regarding unused inputs.
I'm pretty sure, ist is not good to leave one input floating even when CLK_SEL is connected to GND permanentely. But I don't have any proof for it.
I have thought about:
- Power being wasted when the differential input amplifier is switching often due to erratic input values (CLK1 and /CLK1 might gain very close voltage levels and produce switching when superimposed with HF signals)
- As for the same reason as in 1. cross talk may occur and increase jitter on the output.
- The input amplifier might even oscillate and produce EMI on the PCB
Did I miss any possibility or can something be ruled out?
My other question is, what's best practice here?
- Tie /CLK1 to VDD/2 by connecting it to the same voltage divider as /CLK0 (considering the case of single ended CMOS input) and CLK1 to GND.
- Tie both CLK1 and /CLK1 to GND.
- Tie CLK1 to GND and /CLK1 to VDD.
- Something different...
Note: I'm using the differential input version of this device when dealing with single ended signals as well as with differential signals at the input to reduce the number of different parts in the BOM.