3
\$\begingroup\$

I have 9 microcontrollers ATMEGA3208 and I have connected the RX and TX lines of 8 of them in parallel. My configuration is in master-slave. The master microcontroller send data to one of the 8 RX lines but only one of them can respond at a time. The cable length is about 3 to 5 metres between each node.

I have two questions. My test was done with 2 slaves instead of 8. UART at 9600bps.

If I setup the TX lines of the slaves as Open Drain it works fine, but the signal doesn't have steep ramps. I thought this happens due to Pull-up resistors. And I also think that is going to be better with 8 slaves on the bus, right?

Why doesn't that topology work if the TX lines of the slaves are not Open Drain?

I managed to make it work by disabling the transmit of the UART in all of them except one, and it worked fine. I had two slaves, so I disabled the one and left the other. Also I noticed that the edges of the signal was sharper. Why are they sharper in that case?

Regarding resistors: The value of the resistors for both RX and TX lines are 2.7KΩ. However the Open Drain topology would parallel the internal pull-up resistors. According to the datasheet that resistor is about 20KΩ at minimum. So, using a 2.7KΩ in the output would give us a total resistance of 2.52KΩ (20+2.7)/9. And the Open Drain would make a voltage divider 2.52KΩ + 2.7KΩ (Schematic 2). Which means with 8 slaves and Open Drain topology the signal will not go lower than 1V which is the threshold of the low level. Is that correct?

Wouldn't it be better to disable all the internal pull up resistors and place two (let's say: 4.7KΩ) only at the master side?

Distance: What is the maximum baud rate for such distance? I'm a little worried about the signal integrity. The test was done with 9600bps but I didn't notice any significant difference in 4800bps. The distortion of the signal didn't have a difference.

Voltage values are 3.3V for the UART bus.

Schematic 1. (all resistors are 2.7KΩ)

schematic

simulate this circuit – Schematic created using CircuitLab

Schematic 2. (U4, U5, U6, U7, and U8 are omitted for simplicity).

schematic

simulate this circuit

EDIT: Thank you all very much about your answers so far. I wanted to point out that this is a question about UART only. I am not looking for alternative solutions. I'm just trying to find some answers about the above implementation.

EDIT2: Thank you very much for your answers! I ended up modifying a little my schematic. I disabled the internal pullup resistors of the microcontrollers and I placed external ones at the master's board. Their value would be around 1 KOhm to 3 KOhm. I have to do some tests more to decide the final value. I also replaced all series resistors with 130 Ohm.

I tested 5 slaves over 20 metre cable (with pullup 3 KOhm and 130 Ohm series resistors) and it worked fine.

Would it be better to add open drain/open collector line drivers on every TX lines?

schematic

simulate this circuit

\$\endgroup\$
  • \$\begingroup\$ There are a number of good long distance multiplexed bus schemes out there. The two that come to my mind immediately are RS485 and CAN. Both use differential signalling that makes them somewhat resistant to noise, and both of them are well-established and proven. Why reinvent the wheel here? \$\endgroup\$ – TimWescott Aug 28 at 19:33
  • 1
    \$\begingroup\$ It's a tested implementation and it works fine so far. I'm just trying to find out some answers \$\endgroup\$ – MrBit Aug 28 at 19:43
  • \$\begingroup\$ Can you confirm that you have configured your pins open drain and using actual hardware UART and not bit bang software UART? \$\endgroup\$ – Umar Aug 28 at 19:48
  • \$\begingroup\$ It works in RX line, I haven't tested the TX lines yet. The open drain works with 2 slaves so far. \$\endgroup\$ – MrBit Aug 28 at 19:55
  • 1
    \$\begingroup\$ Have you looked into using LIN transceivers? \$\endgroup\$ – filo Aug 28 at 21:02
4
\$\begingroup\$

If I setup the TX lines of the slaves as Open Drain it works fine, but the signal doesn't have steep ramps. I thought this happens due to Pull-up resistors.

Yes. Since the lines are said to be open drain, the lines goes high via charging a \$R*C\$. The capacitance is of the bus and the connected pins and the resistance is the pull-up resistance.

And I also think that is going to be better with 8 slaves on the bus, right?

Yes to some extent (you will be increasing the capacitance in the other hand) but also consider the fact that lower the pull-up resistance higher will be the current the pins has to sink when sending a logic zero.

Why doesn't that topology work if the TX lines of the slaves are not Open Drain?

When the master is in listening state form on of the slave, if all other slave TX pins are in Push Pull state, as soon as slave outputs a low, there will be unwanted high current flowing from all the remaining slave TX pins to the TX pin of the transmitting slave. This is never ever recommended..

Also I noticed that the edges of the signal was sharper. Why are they sharper in that case?

Can you post the waveform? Maybe the UART communication with push pull setting enabled.

And the Open Drain would make a voltage divider 2.52KΩ + 2.7KΩ. Which means with 8 slaves and Open Drain topology the signal will not go lower than 1V which is the threshold of the low level. Is that correct?

Yes. If I assume that the series resistors you have connected are of 2.7 kOhms, then they do form a voltage divider for a logic zero. For logic One, they do not pose significant threat. When a high is sent on the line, there will a tiny bit slightly lower value than VCC. When a logic zero is sent, the level will be about a Volt. Eliminating one series resistor (perhaps connected to master) will bring down the voltage levels into valid range for both logic high and low .
It will also help to increase the bus speed.

What is the maximum baud rate for such distance?

In a ideal no noise world, the baud rate is limited by the bus capacitance and the series resistor you have used. At 9600, the bit period is \$104 us\$ and let us assume we prefer to have rise time and fall time of 10% which will be about \$10 us\$. In this case, the allowed bus capacitance is \$\frac{10us}{ 2.7 kOhms * 3} \$. It depends on the cables used.

The concern about signal integrity. You have got it right.

No world is ideal. The master UARTmay have to implement complex protocols for error checking and so on. I have personally implemented software upgrade feature FPGAs and DSPs present for multiple daughter boards and my best choice was LVDS. They are just channels. You can use UART itself with a new IC in front of UART will automatically translate things to the outside world which are immune to external noise and ground potential offset due to cable resistance and more. Please consider the last point. Explore more options. The final solution will be still UART but the cable just got a immunity option.


Please update all resistor values in the image and any missing voltage values.


Another suggestion to avoid multidrop:use a 1:8 Analog Mux DeMux. Think about it.

\$\endgroup\$
  • \$\begingroup\$ I added a second schematic about what I mean about the voltage devider. \$\endgroup\$ – MrBit Aug 28 at 20:46
  • \$\begingroup\$ All the resistor values in the first schematic are 2.7KΩ \$\endgroup\$ – MrBit Aug 28 at 20:49
  • \$\begingroup\$ Thanks for clarification. I have updated my answer above. In short, the series resistor value is bringing a weak logic zero. \$\endgroup\$ – Umar Aug 29 at 2:45
  • \$\begingroup\$ I saw you didn't edit your answers regarding pull-up resistors in parallel. Aren't they in parallel according to schematic 2? \$\endgroup\$ – MrBit Aug 29 at 6:47
  • \$\begingroup\$ they do are in parallel. i agree. can you point me to where i say it otherwise. i will upcheck it \$\endgroup\$ – Umar Aug 29 at 7:26
1
\$\begingroup\$

RS-485 supports multi-drop topology. This is probably a better choice for your system as it has improved noise immunity and won’t need to be open-drain. It’s the go-to solution for low-speed control networks like you describe.

\$\endgroup\$
  • \$\begingroup\$ RS-485 would need a transceiver which is extra cost for the boards. The solution I described works fine I'm just trying to find out why I see what I see. Also, the slaves don't have to send data at the same time! \$\endgroup\$ – MrBit Aug 28 at 17:15
  • 1
    \$\begingroup\$ Using a direct logic link between your microcontrollers over cables of that length is fraught with noise issues even if it were just point to point. The fact that it is multi drop makes it even worse. \$\endgroup\$ – hacktastical Aug 28 at 17:21
  • \$\begingroup\$ @MrBit - no, the solution you are proposing does not really work across such distance. Don't dismiss the concern and then post yet another question to complain when your own insufficient idea turns out not to work. \$\endgroup\$ – Chris Stratton Aug 29 at 16:24
  • \$\begingroup\$ @ChrisStratton I think my notes have confused you. The schematic above works fine in open drain configuration. It doesn't in push pull, for the obvious reasons. My second question was about a certain thing I witnessed and I didn't want to mix it up with this question cause it was a seperated test with different configuration. \$\endgroup\$ – MrBit Aug 29 at 18:12
  • \$\begingroup\$ @MrBit - no, the only person confused here is you. The schematic above actually will not work reliably over long distances, because source termination is fundamentally unsound in a multdrop setting. Your second question partially illustrates that problem, but only partially - source termination actually can work in a two node setting, but only at the ends which makes it unworkable for a multinode one. \$\endgroup\$ – Chris Stratton Aug 29 at 18:35
1
\$\begingroup\$

TX is an OUTPUT. If they are push/pull, and one TX is high and the other is low, you have a short. If they are open-drain and tied high, any output can pull the entire bus low on it's own, without causing a short.

\$\endgroup\$
  • \$\begingroup\$ That's why I used resistors. Doesn't that prevent the short? \$\endgroup\$ – MrBit Aug 28 at 17:43
  • \$\begingroup\$ @MrBit Then a High on TX1 and a Low on TX0 would send a \$ \frac{ \left( V_{OH}-V_{OL}\right)}{2}\$ \$\endgroup\$ – Scott Seidman Aug 28 at 17:48
  • \$\begingroup\$ That won't happen because the slaves will never transmit at the same time. The implementation is a master-slave mode which makes each slave to transmit data only when the master wants them to do so. The master sends a command to the slave 1, the slave 1 responds back. the others do nothing. \$\endgroup\$ – MrBit Aug 28 at 17:54
  • \$\begingroup\$ The series resistors will prevent the short, but they'll also allow the majority of transmitters that aren't active to block the signal. \$\endgroup\$ – TimWescott Aug 28 at 19:31
  • \$\begingroup\$ If they're push/pull, TX is either 0 or 1, regardless of whether it is transmitting-- it has a value by definition. \$\endgroup\$ – Scott Seidman Aug 28 at 20:35
0
\$\begingroup\$

Lets assume 100 picoFarad per meter for your cabling (twisted pair? coax? etc)

Assume 100 microseconds symbol time (bit time).

Assume you want 63% (one time constant) of final value in 10 microseconds.

We'll use 1,000 ohm Rpullup to make the math easy, then adjust to 2.7Kohm later.

1Kohm and 1nanoFarad is 1uS timeconstant. We can allow 10uS. Thus you can have 10nanoFarad bus capacitance.

10nanoFarad/100pF/meter === 100 meters or 300 feet, at 1Kohm

You have 2.7Kohm, so lets reduce that 100 meters to 100/2,7 or about 40 meters.

This amount of settling (one tau in 1/10 of the bit time) should be very good data link. Depends on sampling at MID_BIT, when the data should be within 1% of final value.

Now----you have interference issues, and ground-upset issues.

\$\endgroup\$

Not the answer you're looking for? Browse other questions tagged or ask your own question.