I have read the I2C bus specification and don't quite understand the limitations of a multi master I2C bus mentioned on page 10: https://www.nxp.com/docs/en/user-guide/UM10204.pdf
One the one hand there is the description in the overview that I2C is a true multi master bus. One the other hand, there is the problem that both master have to identify the rare cases of overlapping access. I think i understood the mechanism during the address phase, but the section ends with the following:
There is an undefined condition if the arbitration procedure is still in progress at the moment when one master sends a repeated START or a STOP condition while the other master is still sending data. In other words, the following combinations result in an undefined condition:
- Master 1 sends a repeated START condition and master 2 sends a data bit.
- Master 1 sends a STOP condition and master 2 sends a data bit.
- Master 1 sends a repeated START condition and master 2 sends a STOP
I found a datasheet and interpret it such that these rare conditions are actually an unsolved problem of I2C multi master operation. http://www.ti.com/lit/ds/symlink/ds90uh947-q1.pdf
The I2C specification does not provide for arbitration between masters under certain conditions.The system should make sure the following conditions cannot occur to prevent undefined conditions on the I2C bus:
... above 3 conditions ...
Note that these restrictions mainly apply to accessing the same register offsets within a specific I2C slave
So how to interpret these 'undefined conditions', how do they occur?
Is I2C by design only capable of handling multiple masters if one can guarantee that both will never access the same slave/slave register?
I found the following in the Atmega datasheet on page 179
Arbitration will continue until only one master remains, and this may take many bits. If several masters are trying to address the same slave, arbitration will continue into the data packet. Note that arbitration is not allowed between:
... 3 conditions ...
It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined.
I'm not sure if they want to say that either
ALL transmissions must be done with the same pattern
just consistently per slave.
I guess they mean the latter in that access to a specific slave should be done by all masters with the same pattern of register read/write, repeated start etc. This would be a way to handle it in practice if multiple master MUST access a slave.
If they meant that any transmission to any slave had to follow one specific pattern, some devices would become unusable (16 bit vs 8 bit data transfer).
Or am i missing something here?