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Let's consider the logical effort methodology for the propagation delay's computation. Here there are some informations (https://en.wikipedia.org/wiki/Logical_effort).

Let's consider a generic CMOS cell, for instance a CMOS NAND. We know that the propagation delay is proportional to the output parasitic capacitance of the cell. But, I was thinking that it should depend also on the input capacitance of the cell: precisely, I thought that the delay should increase if it increases, since high input capacitance mean slower input signal, and so slower output signal.

But if we analyze the delay through the Logical Effort methodology, we get a different result. The normalized delay of a cell is equal to:

enter image description here

where h is the ratio between output and input capacitances. From this formula we see that high input capacitance means small delay. I do not understand the physical cause of this dependence.

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    \$\begingroup\$ This is assuming that the input is driven by a perfect driver. The input capacitance would be a penalty on the preceding driver, not the cell being analyzed. A larger gate (more capacitance) creates a stronger transistor cell, which will be better equipped to drive the output capacitance. \$\endgroup\$
    – Mattman944
    Aug 29, 2019 at 19:10
  • \$\begingroup\$ @Mattman944 - That's what I was thinking too. Why not make it an answer? I'd upvote it! \$\endgroup\$
    – Justin
    Aug 29, 2019 at 20:09
  • \$\begingroup\$ Thank you for the answer. But why larger gate = stronger transistor? I thought that the strength was due only to the ratio W/L \$\endgroup\$
    – Kinka-Byo
    Aug 30, 2019 at 0:21

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From Wikipedia

...electrical effort, h, which is the ratio of the input capacitance of the load to that of the gate.

Take this equation, and lets consider what it means:

\$h=\dfrac{C_{load}}{C_{input}}\$

If a gate, such as an inverter, is driving an identical copy of itself (e.g. same drive strength), and wiring capacitance is neglected, then \$C_{load}=C_{input}\$. The only way to reduce the delay is to drive a smaller load than the input. This can happen if you have a 2x drive strength inverter driving a single 1x strength inverter.

The other issue is that you need to build up to that drive strength. That means that the previous stage now has a larger load, or you are maintaining larger gates throughout the design to take advantage of this in a few specific places.

You can have a h value less than 1, but you will not be able to use that for many gates in any real application.

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  • \$\begingroup\$ But is there a physical reason for the presence of Cinput at the denominator? \$\endgroup\$
    – Kinka-Byo
    Aug 30, 2019 at 0:15
  • \$\begingroup\$ @Kinka-Byo The output capacitance is normalized against the input capacitance. The "default" case is an inverter driving another inverter, both of the same size. You never get to take advantage of increasing the input capacitance, because that increases the Cload of the previous stage. \$\endgroup\$
    – W5VO
    Aug 30, 2019 at 1:16

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