Effects of input capacitance on propagation delay (with Logical Effort analysis)

Question

Let's consider the logical effort methodology for the propagation delay's computation. Here there are some informations (https://en.wikipedia.org/wiki/Logical_effort).

Let's consider a generic CMOS cell, for instance a CMOS NAND. We know that the propagation delay is proportional to the output parasitic capacitance of the cell. But, I was thinking that it should depend also on the input capacitance of the cell: precisely, I thought that the delay should increase if it increases, since high input capacitance mean slower input signal, and so slower output signal.

But if we analyze the delay through the Logical Effort methodology, we get a different result. The normalized delay of a cell is equal to:

where h is the ratio between output and input capacitances. From this formula we see that high input capacitance means small delay. I do not understand the physical cause of this dependence.

Answer 1

From Wikipedia

...electrical effort, h, which is the ratio of the input capacitance of the load to that of the gate.

Take this equation, and lets consider what it means:

\$h=\dfrac{C_{load}}{C_{input}}\$

If a gate, such as an inverter, is driving an identical copy of itself (e.g. same drive strength), and wiring capacitance is neglected, then \$C_{load}=C_{input}\$. The only way to reduce the delay is to drive a smaller load than the input. This can happen if you have a 2x drive strength inverter driving a single 1x strength inverter.

The other issue is that you need to build up to that drive strength. That means that the previous stage now has a larger load, or you are maintaining larger gates throughout the design to take advantage of this in a few specific places.

You can have a h value less than 1, but you will not be able to use that for many gates in any real application.