I have been getting into FPGA programming and Verilog and have been playing around in EDA playground for a bit creating some simple stuff. Often I need a clock so what I do is generate one on the testbench side using:
for (i = 0; i < 1000; i = i+1) begin #10 clk = 1; #10 clk = 0; end
Which works well. Problem is that if I remove the #10, it doesn't work. And I can't figure out why. The reason I'd expect it to work if I remove the #10 statements is because if I am correct, = is blocking in Verilog. (Where <= is not) So to me, it would sound like it should generate a signal as fast as it can. But if I try it in EDA playground, no signals are generated at all. (The signal inspector would just be completely empty)
Does anyone know why?