I need some explanations about the MOSFET parasitic capacitances. Precisely, what I studied is that there are those parasitic capacitances:
But generally in digital electronics texts I see that they are not considered (for instance let's consider a CMOS inverter): there are simply an input capacitance (between input terminal and GND) and an output capacitance (between output terminal and GND).
What is the physical cause of them (for instance we know that CGD is determined by the overlap between the gate and drain metal's etc)? Are they equivalent models of the previous capacitances (and if yes, how do we obtain them)?