always block works only if there's something to "trigger" it. In your example, there were no variables on the RHS of any statements, so
@* effectively reduces to null.
initial would have worked just fine ... or
always begin (without the
And don't forget that you don't need to use
initial — if you have only a single statement, it's perfectly valid to write
initial b <= 1;
always @(posedge clock) data_pipe <= data_in;
From your comment:
I am just trying to learn the difference between reg and wire types in Verilog. I learnt that 'reg' can be used to design combinational circuits like gates. So I think it does not always mean a register. It can be wires too in hardware.
reg does NOT mean "register". It's a very confusing part of Verilog syntax.
reg variables can be assigned to in process blocks (
always statements), while
wire variables are assigned to outside such blocks (
assign statements, module port connections, etc.)