# Verilog code to drive a signal high always

I am learning Verilog fundamentals recently. I want to drive a signal always high using reg. I wrote this and it didn't work.

    reg b;
always@*
begin
b <= 1'b1;
end


b is always 'X' in simulation.

In VHDL, I was able to do similar thing:

signal b: std_logic;
process(all)
begin
b <= '1';
end process;


b is always high in simulation.

I know we can do this using assign statement with wire. But, is it not possible with reg ?

• "always high" and "using registers" makes little sense. – Marcus Müller Aug 30 at 14:42
• I am just trying to learn the difference between reg and wire types in Verilog. I learnt that 'reg' can be used to design combinational circuits like gates. So I think it does not always mean a register. It can be wires too in hardware. – Meenie Leis Aug 30 at 14:54
• Just an observation... In VHDL your 'b <=' 1';' should be a concurrent statement and not in a process. – TonyM Aug 30 at 15:12
• @TonyM I usually write such signals as concurrent statements. But this snippet also did the same job as the concurrent statement when I simulated. I used VHDL-2008. – Meenie Leis Aug 30 at 15:22
• There's a distinction between VHDL and Verilog to.do with initialization that affects signal assignment. VHDL executes each process at least once. First during initialization then potentially during subsequent simulation (and that's not the case here, there are no signals being evaluated here, the sensitivity list derived from the reserved word all is an empty set). For the Verilog implementation you get initialization using an initial statement as in Dave Tweeds answer. (In VHDL you'd declare b as a constant instead.) – user8352 Aug 30 at 23:23

The always block works only if there's something to "trigger" it. In your example, there were no variables on the RHS of any statements, so @* effectively reduces to null.

Of course, initial would have worked just fine ... or always begin (without the @*).

And don't forget that you don't need to use begin/end with always or initial — if you have only a single statement, it's perfectly valid to write

reg b;
initial b <= 1;


or

always @(posedge clock) data_pipe <= data_in;


I am just trying to learn the difference between reg and wire types in Verilog. I learnt that 'reg' can be used to design combinational circuits like gates. So I think it does not always mean a register. It can be wires too in hardware.

No, reg does NOT mean "register". It's a very confusing part of Verilog syntax.

Basically, reg variables can be assigned to in process blocks (initial or always statements), while wire variables are assigned to outside such blocks (assign statements, module port connections, etc.)

In Verilog, you can write

reg b = 1;


And then never make another assignment to it. But that's not a good coding strategy. SystemVerilog simplified the rules and does allow a single assign statement to a variable. You should read this article.

• Hm, so are you saying that we cannot do the same in always block ? – Meenie Leis Aug 30 at 15:24
• You can, but only if there's something to "trigger" the always block. In your example, there were no variables on the RHS of any statements, so @* effectively reduces to null. Of course, initial would have worked just fine ... or always begin (without the @*). – Dave Tweed Aug 30 at 15:41
• Again, SystemVerilog solves this by replacing always @* with always_comb which guarantees to trigger at least once at time 0. – dave_59 Aug 30 at 15:46
• Again, the OP is not asking about SystemVerilog, just plain Verilog. – Dave Tweed Aug 30 at 15:49
• @DaveTweed, I realize that. It helps to explain the problems in Verilog that have been solved by SystemVerilog. And many people still don't realize after 15 years that it's an option available to them. – dave_59 Aug 30 at 15:59