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I am working on a slave device for which I have to write a Master configuration. In the datasheet of the slave, it is mentioned, "The SDO data changes on the falling edge of the SCLK signals. The devices sample the SDI data on the rising edge of SCLK" Can you please tell me the values of CPOL and CPHA for this slave. Thank you

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    \$\begingroup\$ What specific component are you using? It should have a timing diagram that will help a great deal. \$\endgroup\$ Aug 31, 2019 at 12:41
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    \$\begingroup\$ Would strongly suggest you verify any conclusion with a scope or logic analyzer as wrong settings may seem to work but with no margin. \$\endgroup\$ Aug 31, 2019 at 14:46
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    \$\begingroup\$ please use datasheets....cz spi modes have no standard \$\endgroup\$
    – Mitu Raj
    Aug 31, 2019 at 22:16

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This is the first (oldest) answer to this question: Based only on the informations you provided (for a slave device); your statements are equivalent to:

  1. The setup of SDO (Serial Data Out) or MISO (Master In, Slave Out) occurs in the falling edge of SCK.
  2. The sample of SDI (Serial Data In) or MOSI (Master Out, Slave In) occurs in the rising edge of SCK.

This can be either Mode 0 or Mode 3 of SPI. The exact Mode depends on value of SCK in idle state .

Could be:

Mode 0: CPOL =0 (SCK=0 in idle), CPHA =0

Mode 3: CPOL=1, (SCK=1 in idle), CPHA=1

Again: Only based on informations you provided. The doubt would be removed knowing the logic state of SCK pin in idle state (no transmissions).

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    \$\begingroup\$ Thank you Dirceu for making it so easy to understand.. Slave here is MAX149821, I am sharing its spi waveform, please guide further \$\endgroup\$ Sep 3, 2019 at 9:29
  • \$\begingroup\$ Reading datasheet again and taking your comment as a reference, I found the slave configuration to be CPHA=0 and CPOL=0. Please confirm me on this. Slave is MAX14921 \$\endgroup\$ Sep 3, 2019 at 9:43
  • \$\begingroup\$ Yes Lakshya. You're rigth. According the Fig. 7 on MAX14921 datasheet, SPI mode 0 (CPOL=0, CPHA=0) is the correct one. The SCK level in idle state is Low. \$\endgroup\$ Sep 3, 2019 at 11:21
  • \$\begingroup\$ It worked, thank you so much \$\endgroup\$ Sep 4, 2019 at 6:21
  • \$\begingroup\$ If my contribution solved your question (as in fact happened), you could to chosen It as the answer. \$\endgroup\$ Sep 4, 2019 at 9:40
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You must look at master datasheet and slave datasheet to find matching settings. While many microcontrollers have bits named CPOL and CPHA to change settings, there is no single standard how to set these bits to get the settings you need. Different microcontrollers could have different interpretation of these bits, so it is impossible to say how they should be set as we don't even know what the master is.

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  • \$\begingroup\$ This is right. I found inconsistency between modes give by texas and microchip spi chips . Simply matching 'Mode's doesn't to ensure master-slave compatibility. \$\endgroup\$
    – Mitu Raj
    Aug 31, 2019 at 22:15
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Follow the below image carefully. Several times, until you get a gist of it.

SPI timing diagram from Wikipedia

(Image source: Wikipedia - Serial Peripheral Interface)

Thumb rule is as below:

  • CPOL significance: This defines, whether the Clock signal will be high (CPOL = 1) or low (CPOL = 0) before the Chip select goes low (before beginning the transaction).

  • CPHA significance: It tells, whether the data is sampled (by both master and slave) during first edge of the clock signal or the second edge of the clock signal (soon after transaction has started).


Coming to your question:

"The SDO data changes on the falling edge of the SCLK signals. The devices sample the SDI data on the rising edge of SCLK"

this one in particular:

devices sample the SDI data on the rising edge of SCLK

indicates that (referring to the nice waveform)

  1. If CPHA = \$0\$, CPOL has to be \$0\$ so that the sampling can happen during the rising edge of the signal. (RED vertical line).
  2. If CPHA = \$1\$, CPOL has to be \$1\$ so that the sampling can happen during the rising edge of the signal. (Blue vertical line)

So, depending on the options you have in the MCU, you have to choose between Mode 0 or Mode 3. Please share the slave details and we can find it out by looking at the waveforms (timing diagram).

enter image description here


One example:

This is SPI flash from Microchip:
enter image description here

enter image description here

The timing diagram has been given for Mode 3. (notice that the clock is high before the Chip select goes low. Also, notice that the sampling is done on the second active edge (rising edge).

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