2
\$\begingroup\$

In the 4 layer PCB below (top layer) what is better in terms of interference with the analog circuitry on the lower left (current sense amp and buffer op-amp) trace 1 or 2?

The FPGA does have bypass capacitors on the bottom side. The stackup that I'm currently planning to use is 0.8 mm/4 layer (0.035-0.2-0.0175-0.265-0.0175-0.2-0.035)

The traces are from an ADC to an FPGA, the clock frequency is 50MHz. My understanding is that having ground and power planes underneath the traces would make the high frequency component of the signals return under the traces. So placing the traces further away from the analog seems like it might reduce the interference, on the other hand a longer trace is a bigger loop area.

4 layer PCB - top layer - digital trace placement alternatives

\$\endgroup\$
  • \$\begingroup\$ keep them far apart \$\endgroup\$ – analogsystemsrf Aug 31 at 17:36
  • \$\begingroup\$ @analogsystemsrf, you mean #1 on the screenshot? \$\endgroup\$ – axk Aug 31 at 17:37
  • 1
    \$\begingroup\$ If you add a series termination resistor near the driver then that should help regardless of whether you use approach #1 or #2. \$\endgroup\$ – Mr. Snrub Aug 31 at 19:06
3
\$\begingroup\$

placing the traces further away from the analog seems like it might reduce the interference, on the other hand a longer trace is a bigger loop area

You have not shown the power and ground plane. I assume it to be solid underneath the traces as I don't see any other components or via in the region.

  • If there are no more traces to be drawn, go for the one with the least trace length. If hte matching is well done, the interference will be really less.
  • There will be no big loop area even if you go for lengthier trace. Almost all the high-speed currents will be just below the trace. Only disadvantage is that the signal is close to the edge which might be susceptible to external noise.
\$\endgroup\$
2
\$\begingroup\$

Coupling field strength generally falls off at distance squared. If you can make the parasitic loop length increase by less than distance squared (e.g. not a big circle, but linear), then, first order, moving the undesired coupling loop farther away is likely to be a win.

\$\endgroup\$
2
\$\begingroup\$

If you want the cleanest, then laminate the analog trace between 2 ground sections, those sections tied together with dozens of vias.

If you cannot do that, then take the hint from a Howard Johnson book, where he states the Efield coupling ----- over a plane ----- to be proportional to 1/Distance^3

Now for the magnetic coupling over a plane ---- I don't know.

\$\endgroup\$
1
\$\begingroup\$

The return current does spread out on the ground plane beneath the trace, so keeping the traces apart reduces how much of the return currents from both traces overlap each other on the ground plane.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.