I want to estimate power consumption of a battery powered digital circuit that has a CPLD (Lattice LCMXO2-256HC). It receives 64 MHz signal into LVDS input and 10 MHz, 2.5V into a schmitt trigger input. Its output is ~50 kHz so I'm not concerned about the output capacitance. So the question is, how does the input capacitance depend on the input settings, supply voltage, packaging etc or its just the process variation? The datasheet specifies 3-9 pF at 1 MHz, 25°C but that's too broad for me, maybe I can narrow it down somehow?
Most of the capacitance comes from the packaging, and then from the gate/drain/source capacitance of the transistors. I don't think anyone but the manufacturer will be able to narrow the range for you. Someone on the internet may have anecdotal numbers to offer, but the manufacturer is free to change the package or the process at any time as long as the part still falls within the specified range. If you only need a few parts, measure the capacitance yourself.