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I've seen this question: How can I generate a schematic block diagram image file from verilog?, but it talks about verilog, not VHDL. Some answers to that question mention paid tools, and I'm looking exclusively for free, non-commercial tools.

I would like the process to be completely automatic and not manual. I would also like the image to consist purely of logic gates. I've tried researching but I couldn't find anything.

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  • \$\begingroup\$ " I would also like the image to consist purely of logic gates. " I think you need a synthesis tools. All the tools I know which make images from code, use 'behavioral blocks like ADD, SUB, MULT etc. . \$\endgroup\$ – Oldfart Aug 31 '19 at 20:38
  • \$\begingroup\$ ISE can do this but I have to look back to see how I did it since it's a fairly useless feature. It's only good for showing my boss a pretty picture, and all it does is create a block diagram of the modules with the connections in between. No logic gates if you did not code it as logic gates. \$\endgroup\$ – DKNguyen Aug 31 '19 at 21:19
  • \$\begingroup\$ use quartus or vivado for nice block diagram and schematic generation \$\endgroup\$ – Mitu Raj Aug 31 '19 at 22:21
  • \$\begingroup\$ For schematics, the only time that I have seen this to be marginally useful is when we were transitioning from schematic based ASICs to VHDL ASICs and had a hybrid of the two. Gate level schematics generated from VHDL are really, really, hard to understand. So, unless you have a really good reason to do this, I don't recommend it. \$\endgroup\$ – Mattman944 Aug 31 '19 at 23:36
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What you're asking for is a two-step process:

  • Convert HDL to a netlist (a logical description of connectivity)
  • Convert a netlist into a diagram.

HDL (whether that's Verilog or VHDL) to netlist can only be done by a synthesis tool. While there are a few "free" synthesis tools, mostly for specialized applications, most are tied to specific technology vendors.

While converting a schematic to a netlist is fairly straightforward (most any schematic-capture software can produce netlists in a number of formats), converting a netlist into a usable diagram is a hard problem, and I have yet to see a tool, free or otherwise, that does a decent job.

And in the end, such automatically-generated diagrams are rarely useful for any real work anyway.

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