# Ethernet 100 ohm differential pair layout

I'm finishing off the layout of a board in Eagle which has a LAN8710A 100Mbps Ethernet PHY on it. The SMSC documentation is really pretty good but I'm stuck on the important detail of how to do the 100$\Omega$ differential pairs for the Rx/Tx. I understand this is important, but what I don't quite get is how to actually calculate the balanced impedance.

From what I understand, I can use this PCB Impedance and Capacitance Calculator (Microstrip) to calculate the characteristic impedance of the individual traces to make them 50$\Omega$, then use this PCB Impedance and Capacitance Calculator (Differential Microstrip) to calculate the differential impedance of the two tracks routed together. If this is wrong, please somebody point out my error.

However, the bit I don't understand is that both of those calculations require a distance to the ground plane. This is fine for the tracks from the PHY to the magnetics, but the SMSC app notes recommend no planes beneath the tracks from the magnetics to the connector, so how is this supposed to be calculated?

I'm confused. If someone out there can offer me some pointers it'd be much appreciated.

Provide the right resistances on your side of the transformer and put the jack, transformer, and PHY as close as possible to each other. If everything is within a couple inches there is nothing to worry about.

• That's exactly what I'd done. Then I've read the component placement checklist for the LAN8710A and it says at least 0.5" between RJ45 and magnetics and at least 1" between PHY and magnetics. I wanted them a lot closer than that. So now I'm even more confused. – Redeye Oct 26 '12 at 12:36
• @Redeye: Are you really sure it is specifying a minimum distance? If so, is any reason given? I can't think of why minimum separation would be required, except between the network and board sides of the transformer for voltage isolation. But, that's not what you are describing. Show a link to the datasheet that requires this minimum separation. – Olin Lathrop Oct 26 '12 at 13:01
• Yes, it's definitely specifying a minimum. The document is here : www2.smsc.com/mkt/web_lancheck.nsf/… – Redeye Oct 26 '12 at 15:21
• Sorry, should have said - it's on pages 4 and 5. The confusing bit is the first point says "put them as close together as possible". Then it goes on to specify minimum distances, but doesn't give any reason, although I've seen suggestions it's for EMI isolation elsewhere. – Redeye Oct 26 '12 at 15:23
• I've asked the question, I'll see what they come back with. So, to the other part of my question - how do you calculate differential impedance when there's no ground plane to put into the equations for the return path (ie. between RJ45 and magnetics)? – Redeye Oct 26 '12 at 15:54

If you have to use separate magnetics then you could use the same basic spacing and trace widths from the magnetics and over to the RJ45 as you used for the Diff Pair coming from the PHY. Do keep the jack end of the magnetics component as close to the RJ45 as possible.

Note that if you were to use a MagJack (which is an RJ45 with the magnetics built in may be somewhat easier to deal with. Some of these MagJacks require the addition of some components near the RJ45 that get referenced (and/or connected) to a copper pour around the connector pin area. It is common that this pour also have a cutout under it in the PWR and GND layers.

You need to contact your PCB manufacturer to find out what the board stackup is. Then you will know the distance to the ground plane and therefore can set the track width and separation in order to meet the required impedance.

• Welcome to EE.SE. OK answer but missing details and links to answers with similar problems. When answering questions check right-most column for 'related' articles. – Sparky256 Jul 28 '16 at 17:14