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My question is about logic design, that's a subject that I'm studying now, especifically counters and registers. I designed a 8-bit counter using 2 4-bit counters (with load, count and enable signal) as base, but I wonder how to make it count this sequence: 24, 25, ..., 90, 24, 25 never passing through 0-23. How is it possible to making using this two 4-bits counters and some combinational circuits? Can someone help me with that?
First Test P.S I've already tried to do it, but something definitely is wrong, and I didn't figure out what is :/ Thanks in advance for any help :)
KEY[0]=CLOCK KEY1=LOAD SW[0 - 3] = Parallel Load as well as SW [4 - 7] KEY[2] = Count KEY[3] = Synchronous Reset Button LED[0 - 7] = Outputs, and 7 is the MSB

Schematic PDF: https://docdro.id/BiC4q3T

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    \$\begingroup\$ Welcome to EE.SE! This appears to be a homework question. As such, you need to show us your work so far, and explain which part of the question you're having trouble with. For future reference: Homework questions on EE.SE enjoy/suffer a special treatment. We don't provide complete answers, we only provide hints or Socratic questions, and only when you have demonstrated sufficient effort of your own. Otherwise, we would be doing you a disservice, and getting swamped by homework questions at the same time. See also here. \$\endgroup\$ – Dave Tweed Sep 1 at 1:46
  • \$\begingroup\$ Please do share your approach for the solution in detail and point out where exaactly you are astuck. Else, it is not impossible to assume it as a homework only question with no efforts to find solution and close the question. Please elaborate your efforts clearly in the question. \$\endgroup\$ – Umar Sep 1 at 8:00
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As you have a way to load your counters with a value, you would be resetting the upper counter, and loading the lower with 24, 1100b

to load a value you need key[3] high, key[2] high, and Key[1] low, on the next clock edge of Key[0] it will load the value from the SW[0:3] you would have this wired to be 1100b or 24, while for the other counter you would have Key[3] low to reset the counter,

Here is a simulation link for the single counter subsection, to give you an idea what each signal does,

Falstad Circuit Simulator Link

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  • \$\begingroup\$ but when the upper counter reaches 90, how do you get the lower counter back to 24? \$\endgroup\$ – Fernando Santiago Sep 1 at 1:58
  • \$\begingroup\$ Have updated my answer with exactly what you need to do for this style counter, had to simulate it to determine exactly what each key input was doing. \$\endgroup\$ – Reroute Sep 1 at 2:38
  • \$\begingroup\$ Thank you for the example :), but my trouble is to reset the first counter and reload the sequence when it indicates 90, do I need to do a combinational circuit to make it? \$\endgroup\$ – Fernando Santiago Sep 1 at 3:00
  • \$\begingroup\$ Yes, 90 is 01011010b so you will need an 4 input AND gate (possibly built up from a few lesser ones) to trigger that this has happened, at that point you will need to set both counters key states, so that the first is loaded, and the second is cleared, apart from that when the next count arrives it will jump back to 24, the AND gate is no longer valid, and it counts up like normal. \$\endgroup\$ – Reroute Sep 1 at 3:05
  • \$\begingroup\$ are these counters synchronous-load or a-synchronous-load? \$\endgroup\$ – analogsystemsrf Sep 1 at 3:38

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