# 8-bits synchronous up counter with arbitrary sequence

My question is about logic design, that's a subject that I'm studying now, especially counters and registers. I designed an 8-bit counter using 2 4-bit counters (with load, count and enable signal) as base, but I wonder how to make it count this sequence: 24, 25, ..., 90, 24, 25 never passing through 0-23. How is it possible to make this using two 4-bits counters and some combinational circuits? Can someone help me with that?

P.S. I've already tried to do it, but something definitely is wrong, and I didn't figure out what is :/

KEY[0]=CLOCK
KEY[4]=LOAD
SW[0 - 3] = Parallel Load as well as SW [4 - 7]
KEY[4] = Count
KEY[4] = Synchronous Reset Button
LED[0 - 7] = Outputs, and 7 is the MSB

Schematic PDF: https://docdro.id/BiC4q3T (slow, not cropped, no additional information)

• Welcome to EE.SE! This appears to be a homework question. As such, you need to show us your work so far, and explain which part of the question you're having trouble with. For future reference: Homework questions on EE.SE enjoy/suffer a special treatment. We don't provide complete answers, we only provide hints or Socratic questions, and only when you have demonstrated sufficient effort of your own. Otherwise, we would be doing you a disservice, and getting swamped by homework questions at the same time. See also here. Commented Sep 1, 2019 at 1:46
• Please do share your approach for the solution in detail and point out where exaactly you are astuck. Else, it is not impossible to assume it as a homework only question with no efforts to find solution and close the question. Please elaborate your efforts clearly in the question. Commented Sep 1, 2019 at 8:00
• That image is way too small to read. Please post a larger one. Beyond that, there is a general approach for this type of count sequence. Use gates to detect an output of 90, and use that signal to load a 24 into the counter. Commented Jun 29, 2023 at 0:57

## 1 Answer

As you have a way to load your counters with a value, you would be resetting the upper counter, and loading the lower with 24, 1100b

to load a value you need key[3] high, key[2] high, and Key[1] low, on the next clock edge of Key[0] it will load the value from the SW[0:3] you would have this wired to be 1100b or 24, while for the other counter you would have Key[3] low to reset the counter,

Here is a simulation link for the single counter subsection, to give you an idea what each signal does,

Falstad Circuit Simulator Link

• but when the upper counter reaches 90, how do you get the lower counter back to 24? Commented Sep 1, 2019 at 1:58
• Have updated my answer with exactly what you need to do for this style counter, had to simulate it to determine exactly what each key input was doing. Commented Sep 1, 2019 at 2:38
• Thank you for the example :), but my trouble is to reset the first counter and reload the sequence when it indicates 90, do I need to do a combinational circuit to make it? Commented Sep 1, 2019 at 3:00
• Yes, 90 is 01011010b so you will need an 4 input AND gate (possibly built up from a few lesser ones) to trigger that this has happened, at that point you will need to set both counters key states, so that the first is loaded, and the second is cleared, apart from that when the next count arrives it will jump back to 24, the AND gate is no longer valid, and it counts up like normal. Commented Sep 1, 2019 at 3:05
• are these counters synchronous-load or a-synchronous-load? Commented Sep 1, 2019 at 3:38