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When we pick up the datasheets of UC1843B-SP and UCC38C44, we notice that they have the same functional block diagram, specially the PWM generator circuit (Error amplifier, current sensing PIN and the comparotor), the error amplifier of both devices goes through a divider by 3. But when we come the "slope compensation design", we notice that there is a diffence in the design process between the two devices.

*In UC1843B-SP, in page 18/27 of the datasheet, a gain "Gcs=3" is incorporated in the slope compensation design (See equations 46 to 51).

*In UCC38C44, in page 30/50 of the datasheet, we do not see any gain in the design of slope compensation(See equations 31 to 38).

Why there is a difference in the design of current sensing and slope compensation between these devices eventhough they have the same functional block diagrame?

What is the effect of the divider on the output of "Error Amplifier" to the current sensing and slope compensation PIN ?

datasheet of uc1843B-SP: http://www.ti.com/lit/gpn/UC1843B-SP Datasheet of UC38C44 : http://www.ti.com/lit/ds/symlink/ucc38c44.pdf

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There should not be a difference between the two circuits beside the rad-hard qual for one of them provided that the external slope is added to the CS pin. Slope compensation consists of reducing the current loop gain by adding an external positive slope to the CS pin. It helps taming the double sub-harmonic poles located at \$F_{sw}/2\$. If you now decide to subtract the ramp from the CMP pin instead, then yes, the divide-by-three gain enters the picture as it reduces the internal slope effectively applied at the CS comparator.

Rather than taking a portion of the oscillator ramp, it is more rugged to actually build a lower-impedance ramp generator from the DRV pin. It has been implemented by R. Ridley in the 90' I think and has proven to be an excellent solution versus the solution from Unitrode.

The ramp is generated using a simple \$RC\$ network and a switching diode. See the below slide excerpted from this APEC 2018 seminar:

enter image description here

The divide-by-3 circuit affects the loop gain and enlarges the dynamics of the feedback signal: 0 to 3 V to produce a 0-to-1-V setpoint versus no divider which would produce a 1:1 CMP to CS setpoint, constraining the op-amp dynamics. The two series diodes provide a true 0% duty ratio setpoint when the CMP pin falls below \$\approx 1.2\;V\$.

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