I'm in the process of trying to simulate a halt instruction based on some arbitrary value. My circuit design may not follow best practices as I'm disabling the overall or master clock sign with a tristate buffer and a comparator circuit. This is only meant to be used for study and research and isn't meant to be for practical use. So I'm not concerned if this is considered a "bad" implementation design.
What I'm after here is an explanation as to the behavior; the output results that Logisim is giving through its simulation.
I have an image with my circuit in 3 different conditions or states, albeit the last state is a slightly modified version of the original. I'll display the image here first so that you can visually see it's overall design. Then I'll give a brief explanation of the 3 states finishing off with my overall question towards my curiosity and or concern of this unexpected behavior.
-Note- The Registers that I'm using in Logisim are counter type registers 4 bits wide, but this should be obvious from the images.
- Condition A:
- The value in the counter register is at 3. On the next rising edge of the clock, I'm expecting it to go to four then halt as the comparator should return 1 and and through the inverter it should disable the connection of the clock through the tristate buffer. However it doesn't. This is where Condition B comes in.
- Condition B:
- Here I pulsed the clock one full clock cycle and as you can see the value went from 7 straight to 0, and the halt signal as well as the value coming out of the counter are not being compared, so the counter register just loops around.
- Condition C:
- Is a quick hack solution that works or gives the behavior that is desired however, it also appears to be an invalid solution. In Condition C, I tied the output of the comparator and the input into the tristate enable line to 0. As long as I have a non 0 value in the halt signal the circuit works and the counter register reaches the halt signal value, it does count up to that value instead of resetting before hand and the comparator does compare equal and produces a one which does in effect trigger the tristate buffer to turn off or disconnect the clock from the rest of the circuit. This the behavior that I want, however if you look closely you will see read lines in the circuit as multiple values are being sent through the same wire which is an invalid solution.
I have a few general questions regarding this.
Why is the original intended circuit as seen in Conditions A & B not allowing the counter register to count to the desired value and resetting at [n-1]. I've tried this with other values and it does the same thing. Thus the comparator part of the circuit never outputs 1 to disable the clock and why does it appear to work when I tie that same line to a constant 0 as in Condition C?
Shouldn't the original circuit count up to 4, compare the two and return 1 out of the comparator? Is this a potential bug in Logisim?
My other question would be what would be the proper way to design a halt signal in Logisim to stop the master or system clock?