# Curious Behavior In Logisim while trying to mimic a halt instruction

I'm in the process of trying to simulate a halt instruction based on some arbitrary value. My circuit design may not follow best practices as I'm disabling the overall or master clock sign with a tristate buffer and a comparator circuit. This is only meant to be used for study and research and isn't meant to be for practical use. So I'm not concerned if this is considered a "bad" implementation design.

What I'm after here is an explanation as to the behavior; the output results that Logisim is giving through its simulation.

I have an image with my circuit in 3 different conditions or states, albeit the last state is a slightly modified version of the original. I'll display the image here first so that you can visually see it's overall design. Then I'll give a brief explanation of the 3 states finishing off with my overall question towards my curiosity and or concern of this unexpected behavior.

-Note- The Registers that I'm using in Logisim are counter type registers 4 bits wide, but this should be obvious from the images.

• Condition A:
• The value in the counter register is at 3. On the next rising edge of the clock, I'm expecting it to go to four then halt as the comparator should return 1 and and through the inverter it should disable the connection of the clock through the tristate buffer. However it doesn't. This is where Condition B comes in.
• Condition B:
• Here I pulsed the clock one full clock cycle and as you can see the value went from 7 straight to 0, and the halt signal as well as the value coming out of the counter are not being compared, so the counter register just loops around.
• Condition C:
• Is a quick hack solution that works or gives the behavior that is desired however, it also appears to be an invalid solution. In Condition C, I tied the output of the comparator and the input into the tristate enable line to 0. As long as I have a non 0 value in the halt signal the circuit works and the counter register reaches the halt signal value, it does count up to that value instead of resetting before hand and the comparator does compare equal and produces a one which does in effect trigger the tristate buffer to turn off or disconnect the clock from the rest of the circuit. This the behavior that I want, however if you look closely you will see read lines in the circuit as multiple values are being sent through the same wire which is an invalid solution.

I have a few general questions regarding this.

Why is the original intended circuit as seen in Conditions A & B not allowing the counter register to count to the desired value and resetting at [n-1]. I've tried this with other values and it does the same thing. Thus the comparator part of the circuit never outputs 1 to disable the clock and why does it appear to work when I tie that same line to a constant 0 as in Condition C?

Shouldn't the original circuit count up to 4, compare the two and return 1 out of the comparator? Is this a potential bug in Logisim?

My other question would be what would be the proper way to design a halt signal in Logisim to stop the master or system clock?

Why is the original intended circuit as seen in Conditions A & B not allowing the counter register to count to the desired value and resetting at [n-1]?

The resulting 1 from the comparator resets the counter asynchronously. That means, it does not need a rising edge.

Thus the comparator part of the circuit never outputs 1 […]

This is not correct. You just don't see it on 1 because the 1 resets the counter immediately. The counter value of 0 leads to a 0 output of the comparator. So the 1 is there just for a very short moment.

You could use a spike catcher like this one:

[…] why does it appear to work when I tie that same line to a constant 0 as in Condition C?

Well, actually it does not work, it just seems so. If you tie the line to 0 the output of 1 leads to an error which is clearly indicated by the red colour and a value of E. This error propagates to the clock input of the counter blocking any further action.

Is this a potential bug in Logisim?

No.

My other question would be what would be the proper way to design a halt signal in Logisim to stop the master or system clock?

Why did you consider a 3-state-buffer? The output is undefined if disabled when not driven by another source. You could use an OR gate to, well, "gate" the clock. Look:

You use an OR because the clock has just risen and the "off" signal is 1. In other situations you would use an AND or anything else appropriate.

• Okay that seems to make sense; was just trying to understand the behavior of Logisim better. I appreciate the feedback and informative information. The only question I have regarding your answer is; "what's a spike character within Logisim?" I'm unfamiliar with that. – Francis Cugler Sep 2 at 21:02
• Hm, I nowhere mentioned a spike "character," just the spike "catcher" shown. This D flip flop reacts on the rising edge of the spike even if we don't see it on screen. Because of the nature of a spike the flip flop could as well trigger on falling edges. – the busybee Sep 3 at 5:46
• Oh okay I misread it; but still, not sure what a spike catcher is... – Francis Cugler Sep 3 at 10:45
• It catches a spike. In this case it's realized by the D flip flop shown. You can "arm" it by resetting it to 0 through the button. If a spike is on the line connected to its clock it will flip to 1 because its D input is 1. – the busybee Sep 3 at 11:36