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I will use a 2.4GHz transceiver on my new project. The PCB material will be FR-4 with 1.6mm thickness and the connector is a SMA. My doubt is about the RF trace that should have 50 ohms impedance. Using AppCAD 4.0, inputing the parameters shown below I have got a 50 ohms result for Width = 45mils and Gap = 8 mils from RF trace to GND. Also I got almost the same result on the online calculator. Does this combinations (45/8 mils) looks correct for you?

What more can I do to improve my layout? Regards.

AppCad bottom layer top layer enter image description here

transparent view: transparent view

edit: this is my final layout... enter image description here

edit: newer... enter image description here

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  • \$\begingroup\$ I agree with @Elmardus, try to avoid thermal relief at ground pins. \$\endgroup\$ – aparna Sep 2 '19 at 12:38
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Your calculations check out for the given values, but keep in mind that the dielectric constant of FR-4 is not tightly controlled, and may vary between 4.35 and 4.7 between manufacturers [1]. Since your trace length is very short, this variation will not have a big effect (you can try the values in the calculator). For more demanding applications, special high-frequency PCB materials (for example: Rogers RO4000 [2]) are available, however they are much more expensive to produce.

It can be beneficial to disable the thermals around the GND-pin holes of the RF connector. By having a solid ground connection, you reduce the parasitic inductance in the return current path, which will improve your signal integrity.

If you use a coplanar waveguide, the copper pours below and on the sides of the conductor must be strongly referenced to each other. This means putting vias to 'stitch' the top and bottom planes together, along both sides of the conductor, to surround it with the ground connection. This is discussed in [3].

The recommended stitching distance between vias should be at most λ/4, with λ/10 as an optimum. For 2.4GHz this results in a via distance of maximum 3.12cm, with 1.25cm recommended. So, for longer trace lengths and higher frequencies stitching becomes more important than in this case with a very short trace length.

[1] https://en.wikipedia.org/wiki/FR-4 see: dielectric constant permittivity

[2] https://www.rogerscorp.com/documents/726/acs/RO4000-LaminatesData-sheet.pdf

[3] Choose the size of via for shielding and stitching

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  • \$\begingroup\$ When you say "It can be beneficial to disable the thermals around the GND-pin holes of the RF connector. By having a solid ground connection, you reduce the parasitic inductance in the return current path, which will improve your signal integrity.", you wanted to say to use direct connection of the SMA to the ground instead of having thermal relief, right? And I will add more vias also. Thanks for your answer \$\endgroup\$ – abomin3v3l Sep 2 '19 at 8:59
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    \$\begingroup\$ Yes exactly. The thermal relief can make soldering a bit easier, especially if you have a big groundplane connected to the pin and/or an underpowered soldering iron. However, if you can avoid using thermal reliefs and instead use a direct ground connection, you can improve the signal integrity and EMC performance of a circuit. At higher frequencies (>10GHz) it may be essential to use direct connections instead of thermal relief, because the 'spokes' connecting to the vias have a high inductance, making them unable to conduct high frequencie, and thus rendering the vias useless. \$\endgroup\$ – Elmardus Sep 2 '19 at 9:05
  • \$\begingroup\$ Ok, thanks for note this. I will apply this to the layout. \$\endgroup\$ – abomin3v3l Sep 2 '19 at 9:07
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for this short of a distance (under 1/8th of a wavelength) impedance requirements get a lot looser, so on that premise its more than suitable, and lines up with my own calculator.

As to the layout, I cannot particularly fault it, you're keeping good separation between it and other nearby signals, you have vias right next to the signal ground so the return current on the plane on the opposite side does not have a large detour, you have well and truly shotgun blasted your board with ground plane vias.

Only thing I struggle with is spotting where the decoupling capacitor is, for this the decoupling cap should be as close to the pins as you can manage, ideally on the same side as the chip, with its traces on the same side of the board. If it's the pair on the center left, I would at minimum spin around the bottom one, and possibly shift those a bit to make their connections as short as possible to the chip.

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  • \$\begingroup\$ So the 45mils/8mils combination looks correct for you? And ok, I will try to place the capacitors closer to the chip. Thanks \$\endgroup\$ – abomin3v3l Sep 2 '19 at 7:55
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    \$\begingroup\$ Saturn PCB toolkit comes up with 50.5 ohms for your current spacing, 48/8 to be dead on the money, but its already well within margin of error, so you should not have to change it. \$\endgroup\$ – Reroute Sep 2 '19 at 8:02
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To what others have said, I'll add,

  • You probably don't want to let the ground fill in between the pads of your DC-blocking capacitor. This will probably lead to excess capacitance to ground, and degrade the return loss of your RF input.

  • You may want to move the RF connector a bit further away, so that the blocking capacitor doesn't have to be directly underneath it. You need quite a bit of space around the ground legs of the connector to allow for selective wave solder, or for a big fat iron to reach in there (more so now that you've removed the thermal relief).

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  • \$\begingroup\$ thanks for note this. I have removed the copper between the pads of the capacitor, but I can't expand the board size more. new last layout on edit \$\endgroup\$ – abomin3v3l Sep 2 '19 at 16:43

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