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I was creating a circuit using two dual input AND gates into a dual input NOR using three modules and module instantiation.

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The first module is for the AND inputs and the second module is for the NOR. Both of these modules work correctly and this was verified using waveform simulation and checking the truth tables.

When I try to simulate the third module aoi22.v I get an error on this line " orInv2 _orInv2_2 ( ._and1(_and1), ._and2(_and2),.f(f) ); " Missing conneciton for port _and1, _and2. When I take out the .f(f) I get an error Missing connection for port f? Any suggestions on how to fix this?

module and22 (input i1,i2,i3,i4, output _and1,_and2); 
    assign _and1 = i1 & i2;
    assign _and2 = i3 & i4;
endmodule
module orInv2 (input _and1, _and2, output f); 
    assign f = !(_and1 | _and2);
endmodule
module aoi22 ( input i1, i2, i3, i4, output _and1, _and2, f);

    and22 _and22_1 ( .i1(i1), .i2(i2), .i3(i3), .i4(i4) );
    orInv2 _orInv2_2 ( ._and1(_and1), ._and2(_and2),.f(f) ); 

endmodule
\$\endgroup\$
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  • \$\begingroup\$ Hint: In aoi22, _and1 is declared as an output, but nothing is assigning it a value. (Same for _and2) \$\endgroup\$ – The Photon Sep 2 '19 at 19:42
  • \$\begingroup\$ Interesting, I thought that the values of _and1 and _and2 were already being assigned output values as they already have been assigned output values from the and22 module. I will look at that. \$\endgroup\$ – ThePathToEnlightenment Sep 2 '19 at 19:50
  • \$\begingroup\$ You never connected the _and1 signal in aoi22 to the one in the _and22_1 instance of and22. You have to do that explicitly. What behavior would you expect if there were two instances of and22 in the same parent module? \$\endgroup\$ – The Photon Sep 2 '19 at 19:52
  • \$\begingroup\$ Thank you were of a great help! I understand it now. I needed to change and22 _and22_1 ( .i1(i1), .i2(i2), .i3(i3), .i4(i4) ); to and22 _and22_1 ( .i1(i1), .i2(i2), .i3(i3), .i4(i4), ._and1(_and1), ._and2(_and2) );. This way verilog explicitly sees how the _and1 and _and2 from my modules are connected. Without this verilog thinks the two instances of _and1 and _and2 are independent of each other. \$\endgroup\$ – ThePathToEnlightenment Sep 2 '19 at 20:08
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\$\begingroup\$
module and22 (input i1,i2,i3,i4, output _and1,_and2); 
    assign _and1 = i1 & i2;
    assign _and2 = i3 & i4;
endmodule
module orInv2 (input _and1, _and2, output f); 
    assign f = !(_and1 | _and2);
endmodule
module aoi22 ( input i1, i2, i3, i4, output f);
    logic o_and1;
    logic o_and2;

    and22 _and22_1 ( .i1(i1), .i2(i2), .i3(i3), .i4(i4), ._and1(o_and1), ._and1(o_and2) );
    orInv2 _orInv2_2 ( ._and1(o_and1), ._and2(o_and2),.f(f) ); 
endmodule
\$\endgroup\$

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