Let's consider a four-way set-associative cache, just like this one:
As you can see this cache has a read port but there is no write port. I was wondering if you guys could help me figure out how one would implement such a port in this set-associative cache.
I don't think the write method is relevant here, because I'm interested in how a MIPS processor or its memory management unit would write to cache, but if I'm wrong let's say this cache uses the write-back method to write data to main memory.
The book I've taken the picture from also says that caches, rather, SRAMs only have one access port which provides both read and write.