# Path analysis D-FLIP-FLOP - what is SET?

I have to calculate the clock paths in a circuit and I have a 2 dual positive-edge-triggered D-TYPE FLIP-FLOP with clear and reset called DFF1 and DFF2.

what does it mean: the CLR and SET pins of the two flip-flops are set such that {DFF1,DFF2} are reset to {1,0}?

Thanks!

I don't see the sentence you provide in the datasheet. Instead the datasheet says:

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs.

A PRE input sets the Q to 1, a CLR input sets the Q to 0. There are two flip-flops in this chip, so PRE1 and CLR1 are for the first flip-flop while PRE2 and CLR2 are for the second flip-flop.

• this is one of the task for one exam. I didn't know how to interpret this. – tairebit Sep 4 '19 at 14:08
• but from where should I get the SET from the table? – tairebit Sep 4 '19 at 14:31

The only part of the datasheet you will need to look at for this is the truth table. The sentence in your question does not appear in the datasheet you linked, so I could be wrong with your interpretation (assuming that this was the task given to you).

The outputs of the Flip Flop are Q and inverse Q (the one with the line above it). It is (obviously) the inverse of the Q output, so if Q = 1, then inverse Q = 0.

Now look at the left hand section of the truth table. You can see the column with Preset and Clear. The 'H' and 'L' are to indicate high and low (1,0). The CLK is your clock. The up arrow indicates when the positive edge is triggered, and the 'X' is a 'don't care' state. The 'D' is the data in.

All you need to do is match these up to get the outputs you require. So, if you want the Q output as a 1 and inverse Q as a 0 on a high clock pule, consult the truth table. You can see that Preset will need to be High, Clear needs to be High and the data needs to be High.

This table will let you figure out any configuration of the input pins to get the desired output.