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Ok so i am here again, i posted this question some hours earlier and the answer was to use a state machine in order to achieve it. Now the the question is how do i implement it. I would like it to use these 4 signals : S1 <="0001";, S2 <="0011";, S3 <="0011"; , S4 <="0111"; and display them at the same time. From my understanding i should make 4 std_logic_vector, like that :

     s1           : in std_logic_vector(3 downto 0);
     s2           : in std_logic_vector(3 downto 0);
     s3           : in std_logic_vector(3 downto 0);
     s4           : in std_logic_vector(3 downto 0); 

or should i use std_logic_vector(6 downto 0); because i want to input the 7 segment display directly?

The Moore State Machine Code :

use IEEE.STD_LOGIC_1164.ALL;

entity moore_machine is
port (
 clock: in std_logic; --- clock signal
 reset: in std_logic; -- reset input
 sequence_in: in std_logic; -- binary sequence input
 detector_out: out std_logic -- output of the VHDL sequence detector
);
end moore_machine;

architecture Behavioral of moore_machine is
type MOORE_FSM is (Zero, One, OneZero, OneZeroZero, OneZeroZeroOne);
signal current_state, next_state: MOORE_FSM;

begin
-- Sequential memory of the VHDL MOORE FSM Sequence Detector
process(clock,reset)
begin
 if(reset='1') then
  current_state <= Zero;
 elsif(rising_edge(clock)) then
  current_state <= next_state;
 end if;
end process;
-- Next state logic of the VHDL MOORE FSM Sequence Detector
-- Combinational logic
process(current_state,sequence_in)
begin
 case(current_state) is
 when Zero =>
  if(sequence_in='1') then
   -- "1"
   next_state <= One;
  else
   next_state <= Zero;
  end if;
 when One =>
  if(sequence_in='0') then
   -- "10"
   next_state <= OneZero;
  else
   next_state <= One;
  end if;  
 when OneZero => 
  if(sequence_in='0') then
   -- "100"
   next_state <= OneZeroZero;
  else
   next_state <= One;
  end if;  
 when OneZeroZero =>
  if(sequence_in='1') then
   -- "1001"
   next_state <= OneZeroZeroOne;
  else
   next_state <= Zero;
  end if; 
 when OneZeroZeroOne =>
  if(sequence_in='1') then
   next_state <= One;
  else
   next_state <= OneZero;
  end if;
 end case;
end process;
-- Output logic of the VHDL MOORE FSM Sequence Detector
process(current_state)
begin 
 case current_state is
 when Zero =>
  detector_out <= '0';
 when One =>
  detector_out <= '0'; 
 when OneZero => 
  detector_out <= '0'; 
 when OneZeroZero =>
  detector_out <= '0'; 
 when OneZeroZeroOne =>
  detector_out <= '1';
 end case;
end process;
end Behavioral;

and the static 7-Segment 4-Digit code :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; 

entity seven_segments is
port(
    clk       : in  std_logic;
    bcd       : in  std_logic_vector(3 downto 0);   
    dig_pins  : out  std_logic_vector(3 downto 0);   
    segment7  : out std_logic_vector(6 downto 0)   
    );
end entity;



architecture Behavioral of seven_segments is

begin

    BCD_process : process (clk)
    begin
        if rising_edge(clk) then
            case  bcd is
            when "0000"=> segment7 <="1000000";  -- '0'
            when "0001"=> segment7 <="1111001";  -- '1'
            when "0010"=> segment7 <="0100100";  -- '2'
            when "0011"=> segment7 <="0110000";  -- '3'
            when "0100"=> segment7 <="0011001";  -- '4'
            when "0101"=> segment7 <="0010010";  -- '5'
            when "0110"=> segment7 <="0000010";  -- '6'
            when "0111"=> segment7 <="1111000";  -- '7'
            when "1000"=> segment7 <="0000000";  -- '8'
            when "1001"=> segment7 <="0010000";  -- '9'

            when others=> segment7 <="1111111";
            end case;
        end if;
    end process;

    DIG_pins_process : process (clk)
    begin
        if rising_edge(clk) then

        end if;
    end process;

end architecture;
```
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  • \$\begingroup\$ Use counters to control the multiplexing sequence, simpler to design and for others to understand/support than a state machine. \$\endgroup\$ – TonyM Sep 4 '19 at 13:51
  • \$\begingroup\$ Any idea how could i do it with a state machine though? \$\endgroup\$ – Rozakos Sep 4 '19 at 16:17

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