Power-on delay with 555 Timer

Question

I am trying to create a power-on delay with a 555 timer IC. I have never used one of these before and I am finding it a bit tricky to make applications with it - a lot going on.

I found this circuit online

I also saw this from GreatScott showing the internals

My question is in relation to the power-on delay circuit (first picture) above. Initially the 100uF capacitor is fully discharged (0V) , so doesn't that mean that the trigger pin will be low (less than 1/3 Vcc) and thus the flip flop will get set high and thus cause the output to go high -> defeating the entire purpose?

Secondly, how is it possible to measure the 100uF capacitor voltage from the negative terminal, wouldn't that always be 0V?

Is it just me or are these circuits hard to understand at first?

Answer 1

discharged is about 0V, 0V from 6V (where the capacitopr is connected) is 6V, so the input sees a high voltage.

the negative terminal of the capacitpo is not connected ot 0V so it will not always be 0V, but the resistor will try weakly to make the voltage there become 0v.

So, when the 6V is turned on the top end of the capacitor jumps up to 6V and the bottom end follows it upwards, the 555 sees this a s a "high" and turns off the output.

The resistor pulls down on the bottom end of the capacitor charging it, as it charges the difference between the top end and bottom end increases, when it gets to 4V of charge the bottom end voltage is at 2V above 0V and the 555 sees it as low and turns on the output.