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I came across following problem:

In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in
A. Q = 0, Q' = 1
B. Q = 1, Q' = 0
C. Q = 1, Q' = 1
D. Indeterminate states

I (wrongly) felt that answer would be option D, indeterminate state. But it was option C. The explanation given was:

Here we know that the output will be definitely 11. So its not indeterminate. However its invalid.

I understand that this is true for an SR latch.


But now I am thinking when the output will be indeterminate.

Can we call output of a level-triggered JK flip flop (with clock duration more than flip flop delay) to be indeterminate when J=K=1? I know this corresponds to toggle state, but due to race around condition, can we call it indeterminate?

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  • \$\begingroup\$ I wasn't aware that level-triggered JK flip flops could exist. I'm pretty sure they have to be edge-triggered in order to make the toggle state make sense in the first place. \$\endgroup\$ – Hearth Sep 5 '19 at 13:37
  • \$\begingroup\$ Yes, please provide a schematic for your level-triggered JK flip-flop. \$\endgroup\$ – Elliot Alderson Sep 5 '19 at 13:48
  • \$\begingroup\$ I am not aware of the fact that level triggered JK flip flop cannot exist. Is it really so? If yes, why? I read at some sources that they do exist and can cause race around condition. Some websites also say the same. For example, this webpage has section titled "level triggered flip flops". This quora answer says level trigger can cause race around condition. \$\endgroup\$ – anir Sep 5 '19 at 15:07
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Considering any kind of flip flop, yes, there are possibly indeterminate states at the output. The named example, level-triggered JK flip flop, might start to oscillate if the "forbidden" input combination is set. It depends on the technology the circuit is based on, the propagation delay of its gates, the exact timing of all input signals, and so on.

Another possible effect is metastability. This can stay for a indeterminate duration, and even worse produces illegal values "between" 1 and 0. After this unknown time it can finally set on a legal value which is indeterminate; it can be 1 or 0.

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"Indeterminate" means that you do not know what the state is.

A JK latch will toggle its outputs with J=K=1, and you cannot exactly predict how much time each toggling takes, so the final state will indeed be unknown. Furthermore, it is possible that its internal control signals are faster than the output transistors can switch, so in that case, you might not even get a square wave, but an output signal that does not even reach valid logic levels.


Other ways get an indeterminate state are to

  • violate the setup/hold time requirements, so that you do not know whether some J/K input happens to be read as low or high when the clock is processed; or to

  • observe the initial state after power-up, before the flip-flop has been initialized (with asynchronous set/reset) or before some value has been clocked in.

    You can get the same effect with a simpler circuit, like the buffer below: the output state is either high or low, but you don't know which one:

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ The OP is asking about a level-triggered JK flip-flop, not an edge-triggered flip-flop, with the "clock" asserted for longer than the internal propagation delays. \$\endgroup\$ – Elliot Alderson Sep 5 '19 at 13:46
  • \$\begingroup\$ Oops, you are correct. Thanks! \$\endgroup\$ – CL. Sep 5 '19 at 16:14
  • \$\begingroup\$ @Elliott But there are no 'level triggered' flip flops. They are called latches. Flip-flops are edge triggered elements made from two cascaded latches. They are Either rising or falling edge. Op meant JK latch \$\endgroup\$ – Mitu Raj Sep 5 '19 at 16:17
  • \$\begingroup\$ @MituRaj Latches are also known as level-triggered flip flops. They're two words for the same thing. \$\endgroup\$ – Hearth Sep 5 '19 at 16:59
  • \$\begingroup\$ @MituRaj I wish the names "flip-flop" and "latch" had standardized, formal definitions as you suggest but they do not. Different authors use these terms interchangeably. \$\endgroup\$ – Elliot Alderson Sep 5 '19 at 18:54
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Can we call output of a level-triggered JK flip flop (with clock duration more than flip flop delay) to be indeterminate when J=K=1? I know this corresponds to toggle state, but due to race around condition, can we call it indeterminate?

Answer: No

When J=K=Clk=1, the S!,R! Intermediate states will toggle to complement the output states of Q,Q!.

  • The latched SR state of S!=R!=0 is not possible.
  • The State of a latch with S!=R! =0 is not indeterminate as both Q,Q!=1.
    • the unknown in a simple latch is which SR input changes 1st, from above, that determines which output of Q,Q! Changes from 11 to either 10 or 01.
    • but this does not occur in a JK FF. enter image description here

ALSO:

Flip Flops are Clk edge-triggered, which MAY have Latch functions for S,R that are level-dependent

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Have you heard about rule of Flip Flop? (Q and Q` should be the complement of each other)

When both the SET and RESET inputs are low, then the flip flop will be in undefined state. This is because having low inputs on SET and RESET violates the rule of flip-flop that the outputs should complement each other. So the flip-flop is in its undefined state

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    \$\begingroup\$ An undefined state is most certainly not the same as a forbidden state. \$\endgroup\$ – Elliot Alderson Sep 5 '19 at 12:50
  • \$\begingroup\$ Level triggered RS flipflops can and do exist but have a problem that R=S=1 should be avoided. To get around this problem create a JK flipflop from the RS flipflop by simply adding the feedback connections from outputs to inputs. Now J=K=1 is toggle mode rather than forbidden state but the newly created JK flipflop must be edge triggered with a very narrow clock pulse to avoid output oscillations. You can't level trigger a JK flipflop with the exception of master-slave JK flipflops which are pulse triggered. \$\endgroup\$ – James Sep 5 '19 at 17:14

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