I came across following problem:
In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in
A. Q = 0, Q' = 1
B. Q = 1, Q' = 0
C. Q = 1, Q' = 1
D. Indeterminate states
I (wrongly) felt that answer would be option D, indeterminate state. But it was option C. The explanation given was:
Here we know that the output will be definitely 11. So its not indeterminate. However its invalid.
I understand that this is true for an SR latch.
But now I am thinking when the output will be indeterminate.
Can we call output of a level-triggered JK flip flop (with clock duration more than flip flop delay) to be indeterminate when J=K=1? I know this corresponds to toggle state, but due to race around condition, can we call it indeterminate?