When can the output of any flip flop (e.g., JK FF) be indeterminate?

Question

I came across following problem:

In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in
A. Q = 0, Q' = 1
B. Q = 1, Q' = 0
C. Q = 1, Q' = 1
D. Indeterminate states

I (wrongly) felt that answer would be option D, indeterminate state. But it was option C. The explanation given was:

Here we know that the output will be definitely 11. So its not indeterminate. However its invalid.

I understand that this is true for an SR latch.

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But now I am thinking when the output will be indeterminate.

Can we call output of a level-triggered JK flip flop (with clock duration more than flip flop delay) to be indeterminate when J=K=1? I know this corresponds to toggle state, but due to race around condition, can we call it indeterminate?

Answer 1

Considering any kind of flip flop, yes, there are possibly indeterminate states at the output. The named example, level-triggered JK flip flop, might start to oscillate if the "forbidden" input combination is set. It depends on the technology the circuit is based on, the propagation delay of its gates, the exact timing of all input signals, and so on.

Another possible effect is metastability. This can stay for a indeterminate duration, and even worse produces illegal values "between" 1 and 0. After this unknown time it can finally set on a legal value which is indeterminate; it can be 1 or 0.

Answer 2

"Indeterminate" means that you do not know what the state is.

A JK latch will toggle its outputs with J=K=1, and you cannot exactly predict how much time each toggling takes, so the final state will indeed be unknown. Furthermore, it is possible that its internal control signals are faster than the output transistors can switch, so in that case, you might not even get a square wave, but an output signal that does not even reach valid logic levels.

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Other ways get an indeterminate state are to

• violate the setup/hold time requirements, so that you do not know whether some J/K input happens to be read as low or high when the clock is processed; or to

• observe the initial state after power-up, before the flip-flop has been initialized (with asynchronous set/reset) or before some value has been clocked in.

  You can get the same effect with a simpler circuit, like the buffer below: the output state is either high or low, but you don't know which one:

^{simulate this circuit – Schematic created using CircuitLab}

Answer 3

Can we call output of a level-triggered JK flip flop (with clock duration more than flip flop delay) to be indeterminate when J=K=1? I know this corresponds to toggle state, but due to race around condition, can we call it indeterminate?

Answer: No

When J=K=Clk=1, the S!,R! Intermediate states will toggle to complement the output states of Q,Q!.

• The latched SR state of S!=R!=0 is not possible.
• The State of a latch with S!=R! =0 is not indeterminate as both Q,Q!=1.
  • the unknown in a simple latch is which SR input changes 1st, from above, that determines which output of Q,Q! Changes from 11 to either 10 or 01.
  • but this does not occur in a JK FF.

ALSO:

Flip Flops are Clk edge-triggered, which MAY have Latch functions for S,R that are level-dependent

Answer 4

Have you heard about rule of Flip Flop? (Q and Q` should be the complement of each other)

When both the SET and RESET inputs are low, then the flip flop will be in undefined state. This is because having low inputs on SET and RESET violates the rule of flip-flop that the outputs should complement each other. So the flip-flop is in its undefined state