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I recently asked a question that ended up involving answers about an automatic global reset capability that FPGAs have, and though the question got solved, I'm still quite unclear about this, and would like more information. I tried to scour the web, but wasn't able to find satisfactory answers.

1) What exactly is this global reset capability?

2) Why do FPGAs have this capability?

3) How do FPGAs infer this capability?

4) Could you provide an example of code which would have the FPGA infer the global reset, and an example using the same code where the FPGA does not infer the global reset?

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What exactly is this global reset capability?

It's a feature by which all (or some designated set) of the flip-flops in the FPGA fabric will be reset at start up. It would typically happen after the configuration is loaded but before the logic begins operating.

Why do FPGAs have this capability?

This allows the designer to predict (or choose) what state each flip-flop will be in when execution of their logic begins.

How do FPGAs infer this capability?

It doesn't have to be inferred. It's designed in to the hardware so that it happens automatically as part of the process of loading the configuration.

The state that the logic resets to is probably controllable by your code. Details of how may depend on which FPGA vendor and family you are using.

Could you provide an example of code which would have the FPGA infer the global reset, and an example using the same code where the FPGA does not infer the global reset?

In a FPGA that has this feature, it will happen for any code, without needing any particular structures to appear in the code.

If there's a way to disable this feature, how to enforce that will depend on the FPGA vendor. Xilinx, Intel (aka Altera), Lattice, Microchip (aka Microsemi aka Actel), etc., might each offer a different way to do it. It might require instantiating a reset controller instance in the code, or a pragma comment in the code, or a command line flag issued to one of the programs in the tool chain (maybe as late as bitfile generation). It might be disabled by default or even unavailable (hat tip to @JonRB). Consult your vendor's documentation for further information.

Note: in reference to your previous question, disabling global reset would not solve your problem. It might make the occurence of the problem change from day to day, or change when you re-compile your code, without the ability to correct it. You should use a global reset, but program it to reset to the correct value for your state machine.

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  • \$\begingroup\$ Xilinx FPGA have BRAM/flipflips initiated via configuration, Microchip FPGA's do not \$\endgroup\$ – JonRB Sep 6 '19 at 16:48
  • \$\begingroup\$ @JonRB, thanks, I've never used Microsemi. (I assume you mean Microsemi, not Microchip). \$\endgroup\$ – The Photon Sep 6 '19 at 16:51
  • \$\begingroup\$ I mean microchip as microchip bought microsemi (which bought Actel). I almost exclusively use APA/A3P/Igloo2 and I had a very painful month tracking down a random corruption just after powerup which was tracked to an entity that didn't reset its local registers. \$\endgroup\$ – JonRB Sep 6 '19 at 16:52
  • \$\begingroup\$ @JonRB, Thanks, I hadn't realized. Microchip is certainly an all-consuming beast in recent years. \$\endgroup\$ – The Photon Sep 6 '19 at 16:53
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"Global reset" is very specific to the FPGA family, it is closer to performing a fabric reset, ie reconfiguring the device

For Xilinx devices there is a PROGRAM_B

https://www.xilinx.com/support/documentation/user_guides/ug380.pdf

Active-Low asynchronous full-chip reset.

For Microchip Igloo2/SmartFusion there is DEVRST_B

https://www.microsemi.com/document-portal/doc_view/133847-ac406-configuring-igloo2-and-smartfusion2-devices-for-safety-critical-applications-application-note

In SmartFusion2 and IGLOO2 devices, the system controller manages device initialization, programming operations, and handles the system service requests. After power-on-reset or device reset (DEVRST_N) events, the system controller performs the initialization sequence of the I/O banks, FPGA fabric, and MSS or HPMS

NOTE: this might not set all registers/BRAM to zero, some devices will not guarantee the reset state of registers, this is why it is recomended IF the content of register/BRAM is critical that a dedicated reset state is used to predefine the content

NOTE: such inputs should not be used as general purpose reset as the chip can enter a higher power draw state. This input should be reserved for if/when there is a brownout condition on VCORE such that the configuration cannot be guaranteed

https://www.microsemi.com/document-portal/doc_download/129979-ac393-board-and-layout-design-guidelines-for-smartfusion2-soc-and-igloo2-fpgas-application-note

After device power-up, if the application asserts the DEVRST_N pin and there are no decoupling capacitors on the board, additional surge current on VDD may be observed during assertion of DEVRST_N or during a digest check operation. This section describes how to minimize additional surge current during SmartFusion2/IGLOO2 device reset operation. This additional surge current does not occur during device power-up; it is applicable only when DEVRST_N is asserted.

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