What exactly is this global reset capability?
It's a feature by which all (or some designated set) of the flip-flops in the FPGA fabric will be reset at start up. It would typically happen after the configuration is loaded but before the logic begins operating.
Why do FPGAs have this capability?
This allows the designer to predict (or choose) what state each flip-flop will be in when execution of their logic begins.
How do FPGAs infer this capability?
It doesn't have to be inferred. It's designed in to the hardware so that it happens automatically as part of the process of loading the configuration.
The state that the logic resets to is probably controllable by your code. Details of how may depend on which FPGA vendor and family you are using.
Could you provide an example of code which would have the FPGA infer the global reset, and an example using the same code where the FPGA does not infer the global reset?
In a FPGA that has this feature, it will happen for any code, without needing any particular structures to appear in the code.
If there's a way to disable this feature, how to enforce that will depend on the FPGA vendor. Xilinx, Intel (aka Altera), Lattice, Microchip (aka Microsemi aka Actel), etc., might each offer a different way to do it. It might require instantiating a reset controller instance in the code, or a pragma comment in the code, or a command line flag issued to one of the programs in the tool chain (maybe as late as bitfile generation). It might be disabled by default or even unavailable (hat tip to @JonRB). Consult your vendor's documentation for further information.
Note: in reference to your previous question, disabling global reset would not solve your problem. It might make the occurence of the problem change from day to day, or change when you re-compile your code, without the ability to correct it. You should use a global reset, but program it to reset to the correct value for your state machine.