The following circuit is from Texas Instruments: http://www.ti.com/lit/df/tidrb35a/tidrb35a.pdf

What is the math behind the string of six 470k resistors at the MOSFET gate? I know that they are for the 12V zener. If I say that the DC bus voltage is 1200VDC, then I would have (1200-12)/(470k*6) = 421.28 uA. This seems too low for a zener, but as the load for the zener is the FET gate, then no matter how low the current is, right?

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Diagram with crucial balance of circuit shown and that you can actually read when clicked for full size version:

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  • \$\begingroup\$ Is that link correct? I don't see that schematic anywhere. \$\endgroup\$
    – DKNguyen
    Sep 6, 2019 at 19:57
  • \$\begingroup\$ Sorry, I have updated the link. \$\endgroup\$
    – user115094
    Sep 6, 2019 at 19:59
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    \$\begingroup\$ Even though the current seems low, the datasheet for the 12V zener, indicates that at 250uA, the impedance is 550Ohm (Izk, Zzk), that's the knee current and impedance. At that point the voltage won't be the nominal 12V, but it'll be close. Obviously, the more current (e.g. 2mA), the better regulation. Precise regulation may not be as critical as protecting the MOSFET max rating at Vgs. \$\endgroup\$
    – Big6
    Sep 6, 2019 at 20:43
  • 2
    \$\begingroup\$ Regarding math: I fail to see why you subtract 12V from 1200V (in 1200-12)/(470k*6) ). I think the red text 400V-1200V is defined wrt PGND. The connection of the anode of D31 is missing from shown circuit. Your calculation suggest it is connected to PGND, but I doubt it is PGND. If it were, it makes D15 and D16 useless. Another reason is that all PGND labels are drawn at the same line and this trace goes lower. Please show the whole circuit. \$\endgroup\$
    – Huisman
    Sep 6, 2019 at 21:39
  • 1
    \$\begingroup\$ Let's say that, due to the low current, the zener voltage were 10 volts instead of 12. Would that matter? Why? \$\endgroup\$ Sep 9, 2019 at 1:55

4 Answers 4


This is an additional answer. On reflection, this better addresses the main question.


MOSFET ................... STF2N95K5
12V Zener ................. 1SMB59xxBT3G
Transient suppressors PKE400A

The relationship of the resistors to the 12V zener is secondary to their main task and to "the math behind them". The zener turn on characteristics are relatively unimportant. It is required to "turn on sooner or later" at some voltage well above Q1's Vgs_th.

In the condensed diagram below I have omitted some resistors and named the string "R_HV". As others have noted, multiple resistors are used to address voltage rating issues, but this can be teated as a single resistor.
Rhv = R_HV = 6 x 470k = 2820k.
Call Rhv 3 megohm which serves entirely adequately for the following.
Rhv forms a "Mickey Mouse" (Heath Robinson / Rube Goldberg...) constantish current high side driver. At V_HV = 1200 V it provides about I = V/R 1200/3M = 400 uA gate drive for Q1 when Q1_S is driven to ground.
Or about R = V/R = 400/3M = 133 uA when V_HV = 400VDC.

The power supply outputs sum to 50 Watts.
At 400 V Isupply means is 125 mA at 400V at 100% so well under say 200 mA.
Allow say 500 mA peak. (Duty cycle is approximately the inverse of the efficiency modified Vin and Vout x turns ratio for a flyback converter at full cry.)

The MOSFET datasheet fig 10 shows that Vgs of 8V typical is adequate and 10V is very ample. I'll use Vgs = 10V.
The MOSFET has an immensely high Vgs max of 30V - the 12V protection zener is far lower in voltage than necessary for its task.

The MOSFET is stated to have an ultralow gate charge (10 nC, table 5) - and this is so low for this application that they add C42 (4700 pF) to 'slow things down a bit'.

At 133 / 400 uA gate drive the time to charge C42 to 10V is t = CV/i = 4700E-12 x 10 / 133E-6 = 350 uS at Vhv = 400V and about 120 uS at Vhv = 1200 V. That seems ridiculously long. Actual turn on time will be lower as Vgs_th is 3/4/5 V min/typ/max but that still gives about 50 uS start to turn on time at Vhv = 1200V.
Barring me having dropped a 10E3 or so somewhere that's what the results are.
Compared to that the gate charge is small.
Time to charge gate capacitance is about 25 uS at 400 uA. Gate charge effects should be added to the effects of the added capacitor.

And so we get to the 12V zener.
When the gate capacitance and the external capacitor are charged to 10V and the FET is fully enhanced we still have a safety headroom on the gate voltage of Vgsmax - 10V = 20V before Vgsmax is exceeded. It matters very little what the zener voltage stabilises at as long as it's above about 8V, better if its above 10V, and anything above that is very fine.

See my other answer for the protective action provided by D15, D16 - but it has no involvement in this turn on sequence. The clamp on the upper FET gate ensures that the voltage across it does not exceed about 700 to 800 V during turn on (or at any other time).

I'm still not happy with that massive turnon time - but unless I've missed something that seems to be what happens.


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You can find the answer by reading the datasheet.

3 Watt Plastic Surface Mount Zener Voltage Regulators

Vz=12V 5% @ 31 mA = Izt
Zzt = 6.5 Ohms @ Izt
Zzk=550 Ohms @ 0.25mA = 137 mV

I assert ... the drop from “threshold,zt to knee zk” can be crudely estimated as a fixed bulk series R.

Find Threshold Vth or Vzk at the zk “ Zener knee”.
Vz = Vzk(@ Izk=0.25mA) +Izt * Zzt
... = 12V 5% = Vzk + 31mA * 6.5 Ohms.
Vth = 12V +/-0.6 - 0.2V = 11.8V +/-?

In actuality Rs rises from Zzt to Zzk or 6.5 to 550 Ohms from Iz = 31 mA to 0.25mA but normally this model works well down to 10% or 3.1 mA.


Thus the FET gate voltage is protected with slightly less voltage limit than the 12V rating.

From datasheet.
Zener Voltage Regulator Symbol Parameter

  • VZ Reverse Zener Voltage @ IZT
  • IZT Reverse Current
  • ZZT Maximum Zener Impedance @ IZT
  • IZK Reverse Current
  • ZZK Maximum Zener Impedance @ IZK
  • IR Reverse Leakage Current @ VR
  • VR Reverse Voltage
  • IF Forward Current
  • VF Forward Voltage @ IF
  • IZM Maximum DC Zener Current

I suspect the reason why there are 6 off 470K resistors rather than one at around 2M8 is their maximum working voltage rating. With a maximum HT+ of 1200V I imagine it would be hard and expensive to find a single resistor with a maximum working voltage this high. On the other hand 200V is well within the capabilities of standard, readily available devices. There is an answer discussing this rating here.

There is a similar string of 6 off 470K resistors (in pairs) just to the left of the one under discussion. These serve two purposes, they evenly distribute the voltage across the 3 capacitors that are only rated at 450V and they act as discharge resistors when the power is switched off.

  • \$\begingroup\$ The question isn't about why there are six resistors. It's about how the zener diodes can function with such a low current due to said resistors. \$\endgroup\$
    – DKNguyen
    Sep 6, 2019 at 22:43

Looking at the full circuit explains things better:

Below where I refer to "supply" it relates to the high voltage rail when it is at well above 600 volts. At lower voltages the protective balancing action described below is not necessary and if V-HV is ever always much lower (say 400-600V) then Q1 is not strictly necessary and may be bypassed if desired by the two boldly marked DNP links.

D16 and D15 combine to provide a clamp voltage of ABOUT half supply.
The actual voltage is not too crucial as long as it is usefully lower than Vds_max od the MOSFETS used.

When FET Q2 is off then then Q1 and Q2 share the supply voltage between them so do not emit magic smoke. If V_Q1 gets "too high" the two HV zeners nudge it on enough to share the total voltage with Q2.

When Q2 turns on it pulls Q1 source down until it falls slightly below its clamped gate voltage and it turns on.
Zener D31 serves to ensure that Vgs_Q1 is not large enough to damage as it turns on.
The exact value of Vgs is non critical as well as it is well enough above Vgs_th so the FET is well turned on.

If Vds_Q2 ever gets above about half supply at ANY stage the above sequence turns on Q1 enough to balance the voltages. This is true either when both FETs are notionally off or during the turn on or off sequences.


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