I am trying to advance my way into the STM32F103RB, and I don't understand the address space mapping defined in chapter 3.2 in the the STM32F103RB datasheet.

It states:

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space.

The next chapter 3.3 details on where the different pheripherals are segmented in this chunk of memory. It ranges from:

0x4000 0000 to 0xA000 0FFF.

And my GPIOA peripheral exists on the address:

0x4001 0800 to 0x4001 0BFF.

I really don't understand what I am looking at here. The STM32F103RB only has 128KB flash and 20KB RAM. So obviously I am misunderstanding something here, but how should I map the address ranges to memory that I really have available?

  • \$\begingroup\$ Or is it the case that the chip can address 4gb, while there are only very few regions in that 4gb address space that actually map to physcial memory/registers? Thus, that address 0x4001 0800 really is accessible from code, and that I will allow me to define GPIO pins? \$\endgroup\$ – bas Sep 7 '19 at 8:02
  • \$\begingroup\$ Ah the header files of auto generated code by STMcube also confirm it. PERIPH_BASE 0x40000000UL and #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) and #define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL) \$\endgroup\$ – bas Sep 7 '19 at 8:24

It is the same than with your PC really. It has 64-bit address space which supports 16 exabytes of memory, but you only have maybe 32 gigabytes of memory actually installed.

The STM32 memory is divided into few bigger areas like Flash, SRAM, factory boot ROM and peripherals. While each area is very large, it might only contain a small area that is actually used, and in case of peripherals, not all addresses are contiguous.

  • \$\begingroup\$ Right, good one - the comparison to a normal PC. Should've thought of that myself. \$\endgroup\$ – bas Sep 7 '19 at 8:15
  • \$\begingroup\$ Yes, but don't try to take this analogy further. On the STM32F1 there are some low level adaptations where resources appear at a different address than they physically are. But on a PC, 99% of the time resources are addressed by logical addresses that have nothing to do with the physical address and only even map for that process. Only operating system code particularly drivers gets to deal with physical addresses. \$\endgroup\$ – Chris Stratton Sep 7 '19 at 15:17

The address space is the logical range of addresses, which may, or may not, contain physical memory.

There may, or may not, be off-chip expansion that allows you to map some of these addresses to external peripherals.

There may, or may not, be internal peripherals like GPIO pins, or timer registers, mapped into the logical space.

If you write to an address that's not mapped, nothing will be stored. If you read from an address that's not mapped, you will return garbage. Depending on how the processor has been implemented, there may be other effects from accessing non-mapped address space. With a programmable MMU (memory management unit), you can select certain address ranges as valid, and others to cause an interrupt.

  • \$\begingroup\$ Also interesting to read that I am allowed to read/write non existing memory without cause exceptions. \$\endgroup\$ – bas Sep 7 '19 at 8:17
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    \$\begingroup\$ I would not take that for granted. There are designs that throw exceptions if unmapped memory is accessed, be it read or write. Without going through the data sheet of the system in question here, I'd suspect it to be one of those. You could study the data sheet or simply try. \$\endgroup\$ – the busybee Sep 7 '19 at 8:42

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