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I am trying to connect an LVDS output to an 18-bit parallel input. Ser/des ICs like this all state on their datasheets (like on page 12 of the linked datasheet) that before they are able to function they "must initialize the links to and from [a matching ser/des]". Can this matching ser/des not exist and the data be generated from a different device entirely? The data is sent as 0b1 - 16 bits of data - 0b0.

If not, how would I go about deserializing the data? I thought about using an LVDS receiver such as this to recover the LVDS clock (which is also given as an LVDS output) and the data as single-ended signals and an 18-bit counter driving a multiplexer linked to 18 flip-flops. Would that work? I am a bit worried about timing, since the LVDS clock is 18x faster than the reference clock of the data source. Is that the "cleanest" way to go about it? I am trying not to use an FPGA and stick to discrete parts.

Thanks in advance!

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    \$\begingroup\$ LVDS (EIA-644) is a physical-layer electrical specification that doesn't say what signals are being sent differentially at low voltages. What is the layer on top of this that is doing the serialization? \$\endgroup\$ – TimWescott Sep 8 at 17:03
  • \$\begingroup\$ You need to know how the data is encoded. A serializer doesn't just shift out the input bits, it also encodes the bitstream so the deserializer is able to know where the 18-bit word boundaries are. Also, some embed the clock, and some don't. Even if you have a separate clock that doesn't need to be recovered, you won't be able to decode the data unless you know how it is encoded... so you need to add this information to your question. \$\endgroup\$ – peufeu Sep 8 at 17:06
  • \$\begingroup\$ It's encoded as 0b1 - 16 bits of data - 0b0. I'll add it to the question. The serialization is being done by the data source IC (which has no parallel output I can use). \$\endgroup\$ – vaporK Sep 8 at 17:09
  • \$\begingroup\$ What is the serial bit rate? \$\endgroup\$ – peufeu Sep 8 at 17:18
  • \$\begingroup\$ About 490 Mbps (27 MHz clock * 18 bits) \$\endgroup\$ – vaporK Sep 8 at 17:29
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You can avoid the need for the multiplexer and separate flip flops by using a serial to parallel shift register component. Shift registers of this type are available in logic type parts that are four or eight bits in length that can be easily cascaded to achieve the serial length (parallel width) that you need. If you do use discrete logic parts you will have to use devices that are compatible with the serial data rate. Specialized parts may be needed to achieve very high rates.

You would still need some separate logic to detect the framing of the serial data so that you can properly synchronize the serial to parallel register latch pulse.

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  • \$\begingroup\$ Could I also build myself a shift register with 18 DFFs and an 18-bit counter? \$\endgroup\$ – vaporK Sep 8 at 17:42
  • \$\begingroup\$ At a bit rate of over 500 MHz? Not a chance. The 74HC595 is completely inappropriate here; it tops out around 20-25 MHz at 5V. \$\endgroup\$ – duskwuff Sep 8 at 18:08
  • \$\begingroup\$ @duskwuff - The serial data rate was not specified till well after I posted this answer. \$\endgroup\$ – Michael Karas Sep 8 at 19:15
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The image sensor I am using is able to generate sync patterns that allow the deserializer to lock to the data stream being received. This was not specified in the datasheet but on a separate document containing a register reference. Using these sync patterns and connecting the sensor and the deserializer to the same clock should allow for correct deserialization.

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