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it is known that "11" are invalid inputs for a SR Latch. But I do not understand the reason of that. I cannot see the electrical conflict in this structure:

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If R = 1, its NOR gate will give 0, for any value of the other input signal. If S = 1, its NOR gate will give 0, for any value of the other input signal.

So we will get 0 at both output. What is the problem? I may understand that maybe it is not practical useful, but I do not see any conflicts.

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There is no electrical conflict. It is a well defined state, but the conflict is only with the expected logic output because Q will not be /Q as both Q and/Q are 0.

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  • \$\begingroup\$ But which is the problem? Q and /Q are output signals, they are not complementary "given" signal. There is not any imposition on the fact that they must be complementary. I would say simply: in a SR Latch, the output signals are always complementary, except for 11 inputs \$\endgroup\$ – Kinka-Byo Sep 8 at 18:15
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    \$\begingroup\$ @Kinka-Byo There is an assumption that Q and /Q are complementary, and any logic that uses the output of the latch depends on that assumption. It does matter. Also, if you transition directly from this illegal input condition to the hold condition then the state of the latch will be indeterminate. \$\endgroup\$ – Elliot Alderson Sep 8 at 22:18
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There is no conflict. There is nothing wrong with "11" as input to this circuit.

The ONLY problem is that if both inputs change from "1" to "0" simultaneously (whatever that means!), you can't predict the final state of the outputs.

If one changes before the other, then there's still no problem.

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  • \$\begingroup\$ precisely, what will happen if they change from 1 to 0 simultaneously? Q and /Q would oscillate? \$\endgroup\$ – Kinka-Byo Sep 8 at 18:16
  • \$\begingroup\$ No, they won't oscillate, but they could end up in a metastable state for an indefinite amount of time. \$\endgroup\$ – Dave Tweed Sep 8 at 18:17
  • \$\begingroup\$ But which is the cause? If S and R go from 1 to 0, I'd say Q and /Q will be 0. This will mean that immediately both the NOR gates will give 1 for both Q and /Q. So both NOR will have 0 and 1 as inputs, so they will give 0. So they will have 00 as inputs, so they will 1. Is it not correct? \$\endgroup\$ – Kinka-Byo Sep 8 at 18:26
  • \$\begingroup\$ No. Gates don't function in discrete time steps like that. Time is fundamentally continuous -- and so are signals. \$\endgroup\$ – Dave Tweed Sep 8 at 18:37

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