# Preset and Clear in SR Flip Flop

In Practical Electronics for Inventors, Paul states the following as the pulse triggered SR flip flop: Of course there are some minor issues in the truth table. (One of the $$\Q\$$’s must be $$\\overline Q\$$ and $$\00\$$ must be $$\ Q \overline Q\$$ in the hold condition.) But even after correcting them in the back of my mind, I think that the given truth table is not correct for the Set and Preset conditions for the given circuit.

I think that for the circuit shown, $$\\overline{PRE}=0\$$ and $$\\overline{CLR}=1\$$ condition is not correct in the truth table. I think it also depends on the values of $$\S\$$ and $$\R\$$. Like if $$\SR=01\$$ I think $$\Q \overline Q = 11\$$, not $$\10\$$ as the text purports.

Similar concerns for the other non-$$\11\$$ configurations of $$\\overline{PRE} \; \overline{CLR}\$$.

Can you please provide a correct truth table?

Edit: The following is the truth table that I came up with. Please make sure that it is correct.

$$\ \begin{array}{cccc|cc} \overline{PRE} & \overline{CLR} & S & R & Q & \overline Q\\ \hline 1 & 0 & 0 & 0 & Q & 1 \\ 1 & 0 & 0 & 1 & 0 & 1 \\ 1 & 0 & 1 & 0 & 1 & 1 \\ \hline 0 & 1 & 0 & 0 & 1 & \overline Q \\ 0 & 1 & 0 & 1 & 1 & 1 \\ 0 & 1 & 1 & 0 & 1 & 0 \\ \hline 0 & 0 & X & X & 1 & 1 \\ \end{array} \$$

Another Question: I think that this implies that Preset should be activated after activating Set; and Clear, after activating Reset, to have the outputs complements of each other. Correct?

• Might I recommend you edit your question to show the truth table you think it is, worked out by yourself as best you can. The better the quality of your question, the better the quality of the answers you will attract. – TonyM Sep 9 at 13:31
• You might want to search for "practical electronics for inventors errata" to find other typos in the book. – Andrew Morton Sep 9 at 13:33
• If one of the Q's is Qnot, then there can be no 11 or 00, so something must be missing – Scott Seidman Sep 9 at 13:46
• @ScottSeidman Not necessarily. It can't be 11 or 00 in normal operation, but when you do unexpected things they certainly can be. ¬Q is not actually Q through an inverter. – Hearth Sep 9 at 13:47
• @ScottSeidman Not off the top of my head, because this is the sort of behavior that is generally undocumented. You aren't usually supposed to have S and R active at the same time in an SR latch, and the ones I can find that do specify what happens in this case do not have a ¬Q output. However, observe what happens when you drive both S and R low in a normal two-NAND-gate SR latch of the type you find in any basic digital logic textbook: Q and ¬Q both go high. – Hearth Sep 9 at 14:13

One point of confusion here is that the circuit is not a combinational logic block; you can't exactly have a normal truth table. Instead, you have to somehow say what happens relative to the clock edges, possibly over multiple clock edges. That's what the picture of a pulse in the $$\CLK\$$ column is supposed to mean in the book. As a first step, instead of making a single truth table for the entire master/slave combination, I would first make two separate truth tables. The slave truth table should probably have $$\Y\$$, $$\\overline{Y}\$$, $$\CLK\$$, $$\\overline{PRE}\$$ and $$\\overline{CLR}\$$ as inputs. The master truth table would just have $$\S\$$, $$\R\$$, and $$\CLK\$$ as inputs.
I think what you might find is the $$\\overline{PRE}\$$ and $$\\overline{CLR}\$$ function correctly, but only when $$\CLK\$$ is high.
The last line of your truth table is definitely concerning. When $$\PRE\$$ and $$\CLR\$$ are both high (inactive), $$\S\$$ and $$\R\$$ don't matter, and $$\Q\$$ and $$\\overline{Q}\$$ are both high? Are you sure about that? Try re-casting it in terms of $$\Y\$$, $$\\overline{Y}\$$, and $$\CLK\$$ and see if it's still true.