# VHDL design: why my integer goes by the number of bits and not the value?

I am trying to build pwm in wave form .meaning for exmaple I want the pwm go for 5 rising edge on and then 5 rising edges off . But for some reason when I write :

    variable counter_test : integer  range 0 to 10 ;


meaning that variable counter_test should run from 0 to 10 ,so in the waveform it runs from 0 to 15 (my guess is that it runs to 15 becouse 10 in binary form is 1010 ,so it has 4 bits and 2^4-1=15 ) .My question is simple why it runs till 15 and not 10 as I wrote ?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Clock_Divider is
port (
clk_in_27Mhz  : in std_logic ;
clr  : in std_logic;
clk_out_960Hz: out std_logic
);
end Clock_Divider;

architecture logic_clock_divider  of Clock_Divider is

begin

process(clk_in_27Mhz,clr)
variable counter_test : integer  range 0 to 9:=0;

begin

if (clk_in_27Mhz'event and clk_in_27Mhz='1') then
counter_test:=counter_test+1;
if (  0< counter_test and counter_test<4 )  then
clk_out_960Hz<='1';
elsif (  4<counter_test and counter_test<9) then
clk_out_960Hz<='0';

end if;

end if;
end process;

end logic_clock_divider ;


and the waveform is :

why the variable counter_test does not reset at 9 and keeps till 15 ? what is wrong with my code ? and how to fix this problem ?

There's just nothing that would reset the counter_test back to 0.