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Let's consider an op-amp:

enter image description here

From basic courses of electronics, we know that the output voltage as a function of the differential input is given by the following picture:

enter image description here

Now, assuming that:

  • the op-amp is closed with negative feedback;
  • the output voltage has a finite value;
  • the open-loop gain is large enough (ideally infinite);

then

enter image description here

and Vin1 and Vin2 are almost equal (virtual short-circuit).

Question: when I turn on a given circuit containing an op-amp with negative feedback, the op-amp in general will not work exactly and immediately in the linear region of its characteristic. Does the op-amp go into the linear region thanks to the slew rate due to some parasitic capacitors (which are always present)?

This idea has come to my mind after reading the following example taken from Razavi's book:

enter image description here

Thanks to the load capacitor CL indeed we have that the output voltage either increases or decreases and, as a consequence, the difference between the two inputs of the differential pair returns small, thus restoring linearity.

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  • \$\begingroup\$ Should you examine the UA715 opamp schematic, you'll see the use of linearizing resistors in the emitters of the input diffpair. This makes the linear-range 5--10 times larger, and improves the settling behavior. If Bob Widlar was the IC designer, then I'd expect his extensive discrete circuit work for satellites (with Ball Aerospace in Colorado) to have given him the understanding about wider linear range and better settling. \$\endgroup\$ – analogsystemsrf Sep 10 at 15:03
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    \$\begingroup\$ The negative feedback causes it to settle to a linear (non saturated) output despite the slew rate extending the speed it takes to get there. I don't really know where you are going with this question. Slew rate is a dynamic thing and cannot at all be relied upon to cause the two inputs to converge into a stable situation. \$\endgroup\$ – Andy aka Sep 10 at 15:04
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The large swing slew Rate is always limited by drive current limit and load capacitance which near 0 ESR compare to load R.

Thus dV/dt = Ic/C. Where Ic=V/R where for FETs, R = RdsOn or Ron and for BJT drivers , Ic is an active current limiter with the bulk Rce added to it.

Where f(-3dB)=0.35/Tr , and Tr= 10~90% rise time, this is always less than the small signal f-3dB .

Closed loop gain is limited by small internal capacitance and feedback ratio where more -ve feedback results in lower output impedance. Thus more feedback with lower Zout and lower forward gain. Acl*f = GBW.

In other words, for small signals, the Negative feedback (NFB) always reduces the output impedance for small signals which enables mor BW, but for large sig. the slew rate is limited by charge current Ic(max)=dV/dt= V/(R’C’) as the driver becomes saturated and cannot drive any more current to match the input risetime.

BJT OA’ s may have active current limiting of 30mA and slew rate is thus is defined for a fixed load like 30~100pF while FET drivers have Ron limits. Since the cap ESR is lower than the load R, this if often the limiting factor. But then FET’s with lower Ron also higher Coss, so max slew rate includes other variables of the FET & Load pF.

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  • \$\begingroup\$ I tried to edit this answer to make it clearer, but I'm not entirely sure what you are trying to say. You don't describe the first equation (it looks like it may be an impedance), and there are multiple grammatical errors. \$\endgroup\$ – Caleb Reister Sep 10 at 16:53
  • \$\begingroup\$ I edited it to give more clarity on why output impedance and current limits affect slew rate which is inversely related to bandwidth but limited by current for large signals due to rated load capacitance. Capiche? \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 11 at 13:21
  • \$\begingroup\$ I don’t know who or why it was downvoted but this is the correct answer \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 12 at 13:55

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