What does it mean for an output signal to be stable? Is my understanding correct that when an input to a logic circuit changes, the time delay for the signal to reach the output (the time for the output to reflect the change) is directly proportional to the number of gates the signal must pass through? So is it simply that an output is stable when that time delay has finally passed? My textbook uses a 1-bit adder as an example.


Yes, you've got it right. In digital logic, the circuit is stable after it's stopped changing due to a change in the inputs.

the time delay for the signal to reach the output is directly proportional to the number of gates the signal must pass through?

Except for the fact that the delay of different gates might be different, this is correct. For example, an AND gate might have a longer propagation delay than a NAND gate.


As Michael points out in the comments, there are other factors affecting the delay. I answered the question thinking mostly about discrete TTL or CMOS logic designs. Even then, factors like the fan-out from each gate will affect the path delay.

In FPGAs the situation is much more complicated. First because there's no 1-to-1 correspondence between the basic gates (AND, OR, etc.) and the implementation in the FPGA. Second because the speeds you can achieve in an FPGA are much faster than in discrete logic, so relatively small effects start to have a more significant impact in the overall design.

  • \$\begingroup\$ The input to output settling delay can also be affected by the rise time of the input signals and by the delay of the signals along the interconnecting wires. This gets to be particularly important when working in an FPGA environment when attempting to use the part for logic implementation up to the speed rating of the part. Interconnect delays are usually much less of a consideration when using individual gate devices where the delays of the transit paths through the gates are large compared to the signal speeds along the wires. Do note that modern high speed stuff does care about wire speeds \$\endgroup\$ – Michael Karas Oct 29 '12 at 5:23
  • \$\begingroup\$ @MichaelKaras, actually in an FPGA, I'd say the "proportional to the number of gates" rule should be thrown right out the window, because essentially any number of gates, as long as there's no more than 4 or 5 inputs (depending on FPGA family) boil down to a single look-up table when implemented in an FPGA. \$\endgroup\$ – The Photon Oct 29 '12 at 5:36
  • \$\begingroup\$ @Photon - I agree fully with your comment. My comment had the comment about the FPGA environment and then in the next sentence I flipped back to talking about logic gates in individual packages which was probably confusing. \$\endgroup\$ – Michael Karas Oct 29 '12 at 8:04

That is right for combinatorial gates as your title says. If you are dealing with race conditions on the arrival to a flip flop and the setup and hold conditions are not being met then this leads to metastability and in some cases an unknown state can propagate. Or rather the result may not be deterministic.


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