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What are the restrictions on the counting sequence? Give the ROM contents for the following sequences: a) 12, 13, 14, 15, 5, 6, 7, 0, 1, 2, 3, 4, 11, 10, 9, 8, 12, 13, etc... b)8, 9, 0, 1, 8, 9, etc...

This is the question of a sample exam, I have no problem designing a n-bit synchronous counter using any type of flip-flop. My doubts are about the ROM part, on the book I have no example of how to implement a ROM to a counter, can you tell me the step to do it? and I don't get the question of the restrictions of the sequences, do they refer to the pattern (i don't see it) or what do they mean? My last question would be, do I need to design two 4-bit counters?, one for each sequence?

Thanks a lot

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2 Answers 2

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A counter is just a state machine that advances from one state to the next on each clock edge. Normally, you use logic to determine the next state from the current state to create, for example, binary counters, BCD counters or Gray-code counters.

But there's no reason that the next-state logic couldn't be replaced by a ROM. The ROM would be addressed by the state flip-flops, and the output of the ROM would be the next state of the flip-flops. This allows you to create a sequence of states of any length, up to 2N, where N is the number of flip-flops. The states can occur in any order, as long as each state has a unique next state.

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  • \$\begingroup\$ If I understand well what you mean, then the ROM will have in memory the next state of the sequence (no need to calculate the logic equation for each input of the flip-flop). So the outputs of the ROM will be the inputs of the Fli-flop, rigth? and the addresses of the ROM will be each of the states of the flip-flop (what happens with the addresses that are not in use?) \$\endgroup\$
    – user43680
    Commented Oct 30, 2012 at 20:24
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    \$\begingroup\$ If there are addresses not used, you would give them values that put the counter into one of the states in the desired sequence. This allows the counter to recover from starting up in an invalid state. \$\endgroup\$
    – Dave Tweed
    Commented Oct 30, 2012 at 20:55
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Have the D-types in a normal up counter configuration to address the ROM. The ROM would then have any output sequence in order in memory. As counter address new memory location its contents will be addressed and appear on the data bus - your output. Simples.

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  • \$\begingroup\$ But that doesn't address the second sequence... \$\endgroup\$
    – Dave Tweed
    Commented Oct 30, 2012 at 20:05
  • \$\begingroup\$ @DaveTweed Since both sequences are conveniently a power of 2 in length, you can simply repeat the sequence in the ROM. \$\endgroup\$ Commented Oct 31, 2012 at 11:40

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