Verilog: Posedge sensitivity vs. If statement in Always block

Question

I have recently completed a design that had run into timing issues (negative slack). The modules that were found to be troublesome, from the timing reports generated in Vivado 2017.4, are these modules that are used to calculate some synchronous outputs. A clock, reset, and enable (en) signal are provided as inputs. The modules that had these issues were previously implemented as shown below:

always @ (clk, rst) begin
     if (rst) begin
          ...
          ...
     end
     else if (clk & en) begin
          ...
          ...
     end
end

A coworker suggested that the "code is creating latches for the pipeline segments, instead of clocked flip flops". Following his suggestions I changed the modules to what is shown below.

always @ (posedge clk, posedge rst) begin
     if (rst) begin
          ...
          ...
     end
     else if (en) begin
          ...
          ...
     end
end

This seems to have resolved the negative slack coming from these modules, but I am curious to know why this is the case.

Answer 1

A coworker suggested that the "code is creating latches for the pipeline segments, instead of clocked flip flops".

The two code segments are totally different. The first is combinatorial logic, the second is a register.

The behavior of the two is also total different.
In the first what you call a 'clk' is not giving you the behavior of a real clock at all, it is just a signal^*. From the first code you can get gates or latches, but not registers. In the code section you should use blocking = assignments.

The second format should produce registers with an asynchronous positive reset.
In the code section you should use non-blocking <= assignments.

^*_{(That was so unusual that it caused my first, wrong, answer)}

---

I'm just having a hard time seeing why this would be the root of a timing issue.

As you are saying you get negative slack, I assume some other parts of the circuit does have registers in them.
The logic from the first parts of the code has NO registers. It is just one huge combinatorial 'blob'.

my original thinking was that the if-statements would help implement the sequential behavior

No, an if statement produces only multiplexers which are combinatorial again.