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Ambiguous clk in event control error and is pointed to always block.

//fpga4student.com

module PWM_Signals
 (
 input sysclk_p, // 100mhz
 input sysclk_n,
 input reset_n,
 input cpu_restn,
 input increase_duty,
 input decrease_duty,
 output PWM_OUT );

 wire clk; //100mhz
 wire locked;
 wire slow_clk_enable; // slow clock enable signal for debouncing FFs
 reg[31:0] counter_debounce=0;// counter for creating slow clock enable signals
 wire tmp1,tmp2,duty_inc;// temporary flip-flop signals for debouncing the increasing button
 wire tmp3,tmp4,duty_dec;// temporary flip-flop signals for debouncing the decreasing button
 reg[7:0] counter_PWM=0;// counter for creating 10Mhz PWM signal
 reg[7:0] DUTY_CYCLE=128; // initial duty cycle is 50%


 always @(posedge clk or negedge reset_n)
 begin
   if (reset_n == 0)
     counter_debounce <= 0;
   else
     counter_debounce <= counter_debounce + 1;
   if (counter_debounce>=100000000)  
     counter_debounce <= 0;
 end
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Your second if statement isn't controlled by reset_n, which makes it non-synthesizable. You probably meant something more like:

  always @(posedge clk or negedge reset_n) begin
    if (reset_n == 0) begin
      counter_debounce <= 0;
    end else begin
      if (counter_debounce>=100000000) begin
        counter_debounce <= 0;
      end else begin
        counter_debounce <= counter_debounce + 1;
      end
    end
  end
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  • \$\begingroup\$ Thank you Dave. I followed the format you suggested.It worked! \$\endgroup\$ – Thanu Sep 12 at 15:00
  • \$\begingroup\$ @Thanu -- if this solution worked for you make sure to accept that answer by pressing the checkmark on the left side of the answer. \$\endgroup\$ – C. Lange Sep 12 at 15:59

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