I'm working with ALD1106 as part of a circuit I'm testing, but looking at the datasheet for the part, I'm confused by the addition of the V+ pin. It doesn't look like it's tied to anything in the pin out (unlike the V- pin, which seems to just be the NMOS body), so am I supposed to just leave it unconnected?
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Other devices in the series have PMOS transistors and the same pinout for consistency; V+ is used for the substrate contact in those particular cases while V- might be unused. For example, the ALD1105 contains both FET types and uses both pins, while the ALD1107 contains only pFETs and leaves the V- pin unconnected like the question asks. All of these parts put these substrate pins in the same locations on the package.
If the devices are "just" FETs, it should be safe to leave them unconnected. However, given the possiblity that they are used for some kind of ESD protection it may be wiser to connect them to your positive rail, as long as the rail voltage is within the chip's stated/implied operating range of +2 to +12 volts.
answered Sep 13, 2019 at 14:08
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\$\begingroup\$ Thank you for your reply. Your explanation made a lot of sense. Like you said, it should be safe to leave them unconnected, but if we apply a voltage to the pins, assuming that it's for ESD protection and V+ connects to the substrate, it shouldn't affect the operations of the FETs themselves, correct? Earlier, I said I plan to connect V- to the source terminal to eliminate the body effect. \$\endgroup\$ Commented Sep 13, 2019 at 14:19
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\$\begingroup\$ @user101402 without knowing more about the IC, I can't be 100% certain. I would guess that the ESD protection network (if any) will just do nothing with V+ floating, and the only loss of functionality will be that ESD protection. \$\endgroup\$ Commented Sep 13, 2019 at 18:46