I'm trying to design a "double-buffer" structure similar to that used in UARTs (for receiving). In my case, it is for samples from an ADC. I shift them in, and at some point my logic detects a condition that tells me that I want to "save" the block I currently have; thus, a second buffer of type PISO works (serial-out is fine, since the microprocessor can always read the samples from the FPGA sequentially).
A pure HDL solution (using PFUs/LUTs) does not work, because the buffer is too large (I get the "Design does not fit in device selected" error at the mapping stage. Even with the XO2-7000, my required size is slightly larger).
EDIT: I will need 512 elements × 16-bits per element (times two, if we're talking double-buffer). Notice that the ADC has parallel output; the analogy with the UART is not at the bit-level (in the analogy, each bit in a serial transmission would be like each sampled value of the ADC)
IPExpress only offers FIFO (including dual-clock) and RAMs (including dual-port). But ideally, I would need to copy in parallel to the second buffer.
Any suggestions, or pointers to any additional IPs that could do the trick? (doesn't have to be free). The IPs I see through Lattice's website don't seem to match .